Part Number PC87570

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1

- January 1998

Highlights

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�

1998 National Semiconductor Corporation

PRELIMINARY

April 1998

PC87570 Keyboard and Power Management Controller

Highlights

General Description

The PC87570 is a highly integrated embedded RISC-based
controller optimized for power management (PM), keyboard
and mouse (KBC) and system control in portable Personal
Computer (PC) applications.

The PC87570 incorporates National's CompactRISC

TM

CR16A core, a high performance 16-bit RISC processor
core, a Bus Interface Unit (BIU) that directly interfaces with
memory and I/O devices, on-chip memory and system sup-
port functions. Among these are legacy functions, handled
by the Host Bus Interface (HBI), that include the Real-Time
Clock and Advanced Power Control (RTC and APC), and
peripherals, including: frequency-multiplier-based High Fre-
quency Clock Generator (HFCG), Power Mode Control
(PMC), Interrupt Control Unit (ICU), Multi-Input Wake-Up
(MIWU), General Purpose I/O Ports (GPIO) with internal
keyboard matrix scanning, PS/2

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Interface, ACCESS.bus

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(ACB) Interface, two Multi-Function 16-Bit Timers (MFT16),
periodic interrupt timer and WATCHDOG

TM

(TWD), ADC

and DAC.

The PC87570 highly efficient architecture and its on-chip
peripherals, supporting functions and low power consump-
tion, provide a highly integrated solution for portable note-
book PCs, sub-notebook PCs and other portable devices.

Outstanding Features

q

Shared BIOS memory

q

Fully ACPI-compliant embedded controller

q

Proprietary PS/2 shift mechanism

q

Extremely low current consumption in Idle mode

q

Support for a variety of off-chip wake-up sources

q

Scalable design for growth without controller upgrade

Block Diagram

Core Bus

Peripheral Bus

Bus

KBC + PM

Host I/F

RTC +

Processing

Unit

HBI

Host Bus

APC

Host

Config

RAM

Memory

External

BIU

CR16A Core

32.768

ICU

HFCG

PMC

ADC

KBSCAN

ACB

GPIO

WDG

Peripherals

Legacy

ROM

MIWU

IBM

�

, PC-AT

�

and PS/2

�

are registered trademarks of International Business Machines Corporation.

CompactRISC

TM

, WATCHDOG

TM

and TRI-STATE

�

are trademarks of National Semiconductor Corporation.

ACCESS.bus

�

is a registered trademark of Digital Equipment Corporation.

I

2

C

�

is a registered trademark of Philips.

Memory

(ISA Compatible)

MFT16

Timer +

KHz

Adapter

PS/2

I/F

I/F

CLK

DAC

+ I/O

(X2)

2

Highlights

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Features

�

CR16A Core

-- 16-bit embedded RISC processor core

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Bus Interface Unit (BIU)

-- Three address zones for static devices (SRAM,

ROM FLASH, I/O)

-- Configurable wait states and fast read bus cycles

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Internal Memory

-- 2048 bytes of on-chip ROM

-- 1024 bytes of on-chip RAM

-- All memories can hold both code and data

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External Memory

-- Supports BIOS memory (Flash) sharing with PC host

-- Up to 56 Kbyte for code and data

-- Field upgradable with Flash or SRAM devices

-- Supports host controlled code download and update

�

Host Bus Interface (HBI)

-- Three host interface channels, typically used for the

KBC, PM and RTC devices

-- Motherboard Plug and Play (PnP) configuration

o

With Enable and Lock bits for each device

o

Relocatable address for each device

-- Host power supply indicator input pin

-- 8042 KBC standard Interface (60h, 64h)

-- Intel 80C51SL compatible

-- IRQ1 and IRQ12 support

-- Fast Gate A20 and Fast host Reset, via firmware

-- PM interface port (62h, 66h)

-- PM port IRQ11

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Real-Time Clock (RTC) and Advanced Power Control
(APC)

-- RTC

o

DS1287, MC146818 and PC87911 compatible

o

242 bytes battery backed-up CMOS RAM

o

Calendar including century and automatic leap-
year adjustment

o

Optional daylight saving adjustment

o

BCD or binary format for timekeeping

o

Three individually maskable interrupt event
flags: periodic rates from 122

�

s to 500 ms; time-

of-day alarm, once per second to once per day

o

Separate backup battery pin

o

Double buffer time registers

o

The CMOS RAM and the RTC registers can be
accessed by the CR16A firmware

-- APC

o

Alarm wake-up

o

Hardware wake-up events

o

Software off events

�

HFCG

-- On-chip frequency multiplier

-- Single 32.786KHz crystal

-- Software controlled frequency generation

�

PMC

-- 3.3 and 5V operation with mixed voltage system

support

-- Reduced power consumption capability

-- Back-drive protection

-- Three power modes, switched by software or hard-

ware:

o

Active mode operating frequency 4-10MHz

o

Idle (20

�

A)

o

Power Off - RTC only (0.9

�

A typical) from back-

up battery

-- Automatic wake-up on system events

�

ICU

-- 16 maskable interrupt sources

-- Four general purpose external interrupt inputs

-- Programmable trigger mode (level: high or low,

edge: falling or rising)

-- Enable and pending indication for each interrupt

-- Non-maskable interrupt input

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MIWU

-- Supports up to 24 wake-up or interrupt inputs

-- Generates wake-up to PMC

-- Generates interrupts to ICU

-- Provides user-selectable trigger conditions

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GPIO

-- 76 ports

-- I/O pins individually configured as input or output

-- Configurable internal pull-up resistors

-- Special ports for internal keyboard matrix scanning

o

16 open-collector outputs

o

8 Schmidt inputs with internal pull-up

-- Special input for system On/Off switch

-- Supports very low-cost implementation of additional

off-chip I/O ports

�

PS/2 Interface

-- Supports three independent devices (external KBC,

mouse and additional pointing device)

-- Supports byte level handling via hardware accelerator

�

ACB Interface

-- Intel SMBus and Philips I

2

C

�

compatible

-- ACCESS.bus master and slave

-- Supports polling and interrupt controlled operation

-- Generates a wake-up signal on detection of a Start

Condition, while in power-down mode

-- Optional internal pull-up on SDA and SCL pins

3

Highlights

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�

MFT16

-- Two 16-bit timers

-- Each timer supports Pulse Width Modulator (PWM),

Capture and Counter capabilities

�

TWD

-- 16-bit periodic interrupt timer with 30-

�

s resolution

and 5-bit prescaler, for system tick and periodic
wake-up tasks

-- 8-bit WATCHDOG timer

�

ADC

-- Eight channels, 8-bit resolution

-- 10

�

s conversion/channel

-- Internal or external voltage reference

�

DAC

-- Four channels, 8-bit resolution

-- 1

�

s conversion time for 50 pF load

-- Full output range from AGND to AVCC

�

Supports Microsoft Advanced Power Management
(APM) specifications revision 1.2, February 1996

-- Generates the System Management Interrupt (SMI)

�

160-pin PQFP and 176-pin TQFP packages

Basic Configuration

or

Clock

External

Memory

PC87570

Host System Bus (ISA Compatib

le)

32KX1/32KCLKIN

32KX2

HMR

HA18-0

HD7-0

HIOR
HIOW

IRQ1

IRQ11
IRQ12

RD

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0
PB7-0

PC7-0
PD7-0

HIOCHRDY

RTC

Battery

V

BAT

IRQ8

PSCLK1

PSDAT1

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC

AGND

VCC

GND

Power

Supply

SCL

D7-0

HMEMRD

HMEMWR

PSCLK2

PSDAT2

PSCLK3

PSDAT3

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM
HRMS

Configuration

Inputs

I/O

Expansion

TA

HDEN
TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

Interface

Interface

HRSTO

SELIO

(Matrix)

SDA

TB

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

NC
NC

SEL1

NC

(Application)

V

REF

ADC

DAC

4

Table of Contents

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Table of Contents

Highlights

....................................................................................................................................................... 1

1.0

Introduction

1.1

INTERNAL ARCHITECTURE .................................................................................................... 14

1.1.1

Processing Unit ........................................................................................................... 14

1.1.2

BIU ............................................................................................................................... 14

1.1.3

Memory ........................................................................................................................ 14

1.1.4

HBI ............................................................................................................................... 14

1.1.5

Peripherals .................................................................................................................. 14

1.2

EXPANSION OPTIONS ............................................................................................................. 15

1.3

OPERATING ENVIRONMENTS ................................................................................................ 15

1.3.1

IRE Environment ......................................................................................................... 16

1.3.2

IRD Environment ......................................................................................................... 17

1.3.3

DEV Environment ........................................................................................................ 18

2.0

Signal/Pin Connection and Description

2.1

CONNECTION DIAGRAMS ...................................................................................................... 19

2.2

SIGNAL/PIN DESCRIPTIONS ................................................................................................... 21

2.3

RESET SOURCES AND TYPES ............................................................................................... 26

2.3.1

Power-Up Reset .......................................................................................................... 26

2.3.2

Warm Reset ................................................................................................................. 26

2.3.3

WATCHDOG Reset ..................................................................................................... 26

2.3.4

Triggering Reset .......................................................................................................... 26

2.4

STRAP PINS ............................................................................................................................ 26

2.4.1

Setting the Environment .............................................................................................. 26

2.4.2

Other Strap Pin Settings .............................................................................................. 26

2.4.3

System Load on Strap Pins ......................................................................................... 27

2.4.4

Strap Inputs During Idle Mode ..................................................................................... 27

2.4.5

Strap Pin Status Register (STRPST) ........................................................................... 27

2.5

ALTERNATE FUNCTIONS ........................................................................................................ 27

2.6

SYSTEM CONFIGURATION REGISTERS ............................................................................... 29

2.6.1

Module Configuration Register (MCFG) ...................................................................... 29

2.6.2

PAGE Register ............................................................................................................ 30

2.7

SHARED MEMORY CONFIGURATION ................................................................................... 30

2.8

MEMORY MAP .......................................................................................................................... 30

2.8.1

Accessing Base Memory ............................................................................................. 31

2.8.2

Accessing External Memory ........................................................................................ 32

2.8.3

Accessing I/O Expansion Space ................................................................................. 33

3.0

Bus Interface Unit (BIU)

3.1

FEATURES ................................................................................................................................ 34

3.2

FUNCTIONAL DESCRIPTION .................................................................................................. 34

3.2.1

Interfacing .................................................................................................................... 34

3.2.2

Static Memory and I/O Support ................................................................................... 34

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3.2.3

Byte Accessing ............................................................................................................ 34

3.3

CLOCK AND BUS CYCLES ...................................................................................................... 34

3.3.1

Clock Cycles ................................................................................................................ 34

3.3.2

Control Signals ............................................................................................................ 35

3.3.3

Early Write Bus Cycle .................................................................................................. 36

3.3.4

Late Write Bus Cycle ................................................................................................... 38

3.3.5

Normal Read Bus Cycle .............................................................................................. 40

3.3.6

Fast Read Bus Cycle ................................................................................................... 42

3.3.7

I/O Expansion Bus Cycles ........................................................................................... 43

3.3.8

I/O Expansion Example ............................................................................................... 44

3.4

DEVELOPMENT SUPPORT ..................................................................................................... 44

3.4.1

Bus Status Signals ...................................................................................................... 44

3.4.2

Core Bus Monitoring .................................................................................................... 44

3.5

BIU REGISTERS ....................................................................................................................... 45

3.5.1

BIU Configuration Register (BCFG) ............................................................................ 45

3.5.2

I/O Zone Configuration Register (IOCFG) ................................................................... 45

3.5.3

Static Zone Configuration Register (SZCFGn) ............................................................ 45

3.6

USAGE HINTS .......................................................................................................................... 46

4.0

On-Chip Memory

4.1

INTERNAL RAM ........................................................................................................................ 47

4.2

INTERNAL ROM ........................................................................................................................ 47

4.2.1

Access Times .............................................................................................................. 47

4.2.2

ROM Shadow .............................................................................................................. 47

5.0

Host Bus Interface (HBI)

5.1

FEATURES ................................................................................................................................ 48

5.2

HOST ACCESS TO SHARED MEMORY DEVICE ................................................................... 49

5.2.1

Enabling Shared Memory Mode .................................................................................. 49

5.2.2

Memory Device Interface ............................................................................................. 49

5.2.3

Host Access to Shared Memory .................................................................................. 49

5.3

CORE ACCESS TO RTC/APC .................................................................................................. 49

5.3.1

Host and CR16A Arbitration over RTC/APC ............................................................... 49

5.4

USAGE HINTS .......................................................................................................................... 49

5.4.1

Shared Memory ........................................................................................................... 49

5.4.2

Wake-Up from Host ..................................................................................................... 50

5.4.3

Host Power-on Indication ............................................................................................ 50

5.5

HOST ACCESS TO PC87570 RESIDENT I/O DEVICES ......................................................... 50

5.5.1

Host Access to Configuration Registers ...................................................................... 50

5.5.2

Host Access to Resident I/O Devices .......................................................................... 50

5.5.3

Host Bus I/O Cycles .................................................................................................... 50

5.6

KBC CHANNEL ......................................................................................................................... 50

5.6.1

Status Register ............................................................................................................ 50

5.6.2

DBBOUT Register ....................................................................................................... 51

5.6.3

DBBIN Register ........................................................................................................... 51

Document Outline

• General Description
• Outstanding Features
• Features
• Table of Contents
  • Introduction
  • Signal/Pin Connection and Description
  • Bus Interface Unit (BIU)
  • On-Chip Memory
  • Host Bus Interface (HBI)
  • Real-Time Clock (RTC) and Advanced Power Control (...
  • High Frequency Clock Generator (HFCG)
  • Power Mode Control (PMC)
  • Interrupt Control Unit (ICU)
  • Multi-Input Wake-Up (MIWU)
  • General Purpose I/O (GPIO) Ports
  • PS/2 Interface
  • ACCESS.bus (ACB) Interface
  • Multi-Function 16-Bit Timer (MFT16)
  • Timer and WATCHDOG (TWD)
  • Analog to Digital Converter (ADC)
  • Digital to Analog Converter (DAC)
  • Development System Support
  • Device Specifications
  • CR16A Register Map
  • Bootloader Description
• Introduction
  • 1.1 INTERNAL ARCHITECTURE
    • 1.1.1 Processing Unit
    • 1.1.2 BIU
    • 1.1.3 Memory
    • 1.1.4 HBI
    • 1.1.5 Peripherals
  • 1.2 EXPANSION OPTIONS
  • 1.3 OPERATING ENVIRONMENTS
    • 1.3.1 IRE Environment
    • 1.3.2 IRD Environment
    • 1.3.3 DEV Environment
• Signal/Pin Connection and Description
  • 2.1 CONNECTION DIAGRAMS
  • 2.2 SIGNAL/PIN DESCRIPTIONS
  • 2.3 RESET SOURCES AND TYPES
    • 2.3.1 Power-Up Reset
    • 2.3.2 Warm Reset
    • 2.3.3 WATCHDOG Reset
    • 2.3.4 Triggering Reset
  • 2.4 STRAP PINS
    • 2.4.1 Setting the Environment
    • 2.4.2 Other Strap Pin Settings
    • 2.4.3 System Load on Strap Pins
    • 2.4.4 Strap Inputs During Idle Mode
    • 2.4.5 Strap Pin Status Register (STRPST)
  • 2.5 ALTERNATE FUNCTIONS
  • 2.6 SYSTEM CONFIGURATION REGISTERS
    • 2.6.1 Module Configuration Register (MCFG)
    • 2.6.2 PAGE Register
  • 2.7 SHARED MEMORY CONFIGURATION
  • 2.8 MEMORY MAP
    • 2.8.1 Accessing Base Memory
    • 2.8.2 Accessing External Memory
    • 2.8.3 Accessing I/O Expansion Space
• Bus Interface Unit (BIU)
  • 3.1 FEATURES
  • 3.2 FUNCTIONAL DESCRIPTION
    • 3.2.1 Interfacing
    • 3.2.2 Static Memory and I/O Support
    • 3.2.3 Byte Accessing
  • 3.3 CLOCK AND BUS CYCLES
    • 3.3.1 Clock Cycles
    • 3.3.2 Control Signals
    • 3.3.3 Early Write Bus Cycle
    • 3.3.4 Late Write Bus Cycle
    • 3.3.5 Normal Read Bus Cycle
    • 3.3.6 Fast Read Bus Cycle
    • 3.3.7 I/O Expansion Bus Cycles
    • 3.3.8 I/O Expansion Example
  • 3.4 DEVELOPMENT SUPPORT
    • 3.4.1 Bus Status Signals
    • 3.4.2 Core Bus Monitoring
  • 3.5 BIU REGISTERS
    • 3.5.1 BIU Configuration Register (BCFG)
    • 3.5.2 I/O Zone Configuration Register (IOCFG)
    • 3.5.3 Static Zone Configuration Register (SZCFGn)
  • 3.6 USAGE HINTS
• On-Chip Memory
  • 4.1 INTERNAL RAM
  • 4.2 INTERNAL ROM
    • 4.2.1 Access Times
    • 4.2.2 ROM Shadow
• Host Bus Interface (HBI)
  • 5.1 FEATURES
  • 5.2 HOST ACCESS TO SHARED MEMORY DEVICE
    • 5.2.1 Enabling Shared Memory Mode
    • 5.2.2 Memory Device Interface
    • 5.2.3 Host Access to Shared Memory
  • 5.3 CORE ACCESS TO RTC/APC
    • 5.3.1 Host and CR16A Arbitration over RTC/APC
  • 5.4 USAGE HINTS
    • 5.4.1 Shared Memory
    • 5.4.2 Wake-Up from Host
    • 5.4.3 Host Power-on Indication
  • 5.5 HOST ACCESS TO PC87570 RESIDENT I/O DEVICES
    • 5.5.1 Host Access to Configuration Registers
    • 5.5.2 Host Access to Resident I/O Devices
    • 5.5.3 Host Bus I/O Cycles
  • 5.6 KBC CHANNEL
    • 5.6.1 Status Register
    • 5.6.2 DBBOUT Register
    • 5.6.3 DBBIN Register
  • 5.7 PM CHANNEL
  • 5.8 RTC/APC CHANNEL
  • 5.9 CR16A INTERRUPTS
  • 5.10 HOST INTERRUPTS
    • 5.10.1 IRQ1, IRQ12 and IRQ11 and IRQ8 Buffers
  • 5.11 SYSTEM CONSIDERATIONS
    • 5.11.1 Reset Configuration
    • 5.11.2 Host Power-On (HPWRON) Indication Input
    • 5.11.3 Host Master Reset (HMR) Input
    • 5.11.4 Host Reset Output (HRSTO) from PC87570
    • 5.11.5 HDEN Strap
    • 5.11.6 GA20 Pin Functionality
    • 5.11.7 Host Driven Wake-Up
    • 5.11.8 APC-ON and APC-OFF Events
  • 5.12 HBI REGISTERS ACCESSED BY CR16A
    • 5.12.1 Control and Status Register 1 (CST1)
    • 5.12.2 Control and Status Register 2 (CST2)
    • 5.12.3 RTC Core Address Register (RTCCA)
    • 5.12.4 RTC Core Data Register (RTCCD)
    • 5.12.5 Host PnP Initial Configuration Base Address...
    • 5.12.6 Host Interface Control Register (HICTRL)
    • 5.12.7 Host Interface IRQ Control Register (HIIRQC...
    • 5.12.8 Host Interface KBC Status Register (HIKMST)...
    • 5.12.9 Host Interface Keyboard Data Out Buffer Reg...
    • 5.12.10 Host Interface Mouse Data Out Buffer Regis...
    • 5.12.11 Host Interface KBC Data In Buffer Register...
    • 5.12.12 Host Interface PM Port Status Register (HI...
    • 5.12.13 Host Interface PM Data Out Buffer Register...
    • 5.12.14 Host Interface PM Data In Buffer Register ...
  • 5.13 HOST CHANNEL CONFIGURATION
    • 5.13.1 Chip Base Address Initial Setting
    • 5.13.2 Operation Guidelines
  • 5.14 HBI REGISTERS ACCESSED BY HOST
    • 5.14.1 Identification Register (SID)
    • 5.14.2 Identification Type Register (SIDT)
    • 5.14.3 Identification Revision Register (SIDR)
    • 5.14.4 Base Address High Register (SBAH)
    • 5.14.5 Base Address Low Register (SBAL)
    • 5.14.6 RTC Chip Select Address High Register (RTC...
    • 5.14.7 RTC Chip Select Address Low Register (RTCC...
    • 5.14.8 KBC Chip Select Address High Register (KBC...
    • 5.14.9 KBC Chip Select Address Low Register (KBCC...
    • 5.14.10 PM Chip Select Address High Register (PMC...
    • 5.14.11 PM Chip Select Address Low Register (PMCS...
    • 5.14.12 Function Enable Register (FER)
    • 5.14.13 Function Lock Register (FLR)
    • 5.14.14 IRQ Enable Register (IRQE)
• Real-Time Clock (RTC) and Advanced Power Control (...
  • 6.1 FEATURES
  • 6.2 RTC FUNCTIONAL DESCRIPTION
    • 6.2.1 Host Bus Interface
    • 6.2.2 Core Bus Interface
    • 6.2.3 Bank Description
    • 6.2.4 Bank Accessing
    • 6.2.5 RTC Clock Generation
    • 6.2.6 Internal Oscillator
    • 6.2.7 External Oscillator
    • 6.2.8 Timing Generation
    • 6.2.9 Timekeeping
    • 6.2.10 Updating
    • 6.2.11 Alarms
    • 6.2.12 Power Supply
    • 6.2.13 System Bus Lockout
    • 6.2.14 Power-Up Detection
    • 6.2.15 Oscillator Activity
    • 6.2.16 Interrupt Handling
    • 6.2.17 Battery-Backed Register Banks and RAM
  • 6.3 RTC REGISTERS
    • 6.3.1 RTC Control Register A (CRA)
    • 6.3.2 RTC Control Register B (CRB)
    • 6.3.3 RTC Control Register C (CRC)
    • 6.3.4 RTC Control Register D (CRD)
  • 6.4 USAGE HINTS
  • 6.5 APC FUNCTIONAL DESCRIPTION
    • 6.5.1 Operation
    • 6.5.2 User Selectable Parameters
    • 6.5.3 System Power States
    • 6.5.4 System Power Switching Logic
    • 6.5.5 APC-ON/APC-OFF Interrupt Signals
    • 6.5.6 Entering Power States
    • 6.5.7 Predetermined Wake-Up
    • 6.5.8 Ring Signal Event
  • 6.6 APC REGISTERS
    • 6.6.1 APC Control Register 1 (APCR1)
    • 6.6.2 APC Control Register 2 (APCR2)
    • 6.6.3 APC Status Register (APSR)
    • 6.6.4 RAM Lock Register (RLR)
  • 6.7 REGISTER BANKS
• High Frequency Clock Generator (HFCG)
  • 7.1 FEATURES
  • 7.2 FUNCTIONAL DESCRIPTION
    • 7.2.1 Setting Clock Frequency
    • 7.2.2 Fast Clock Setting
  • 7.3 HFCG REGISTERS
    • 7.3.1 HFCG Control Register (HFCGCTRL)
    • 7.3.2 HFCGM Low Value Register (HFCGML)
    • 7.3.3 HFCGM High Value Register (HFCGMH)
    • 7.3.4 HFCGN Value Register (HFCGN)
    • 7.3.5 HFCGI Low Value Register (HFCGIL)
    • 7.3.6 HFCGI High Value Register (HFCGIH)
• Power Mode Control (PMC)
  • 8.1 FEATURES
  • 8.2 THE POWER MODES
  • 8.3 SWITCHING BETWEEN POWER MODES
    • 8.3.1 Decreasing Power Consumption
    • 8.3.2 Increasing Performance
  • 8.4 POWER MODE CONTROL REGISTER (PMCR)
  • 8.5 USAGE HINTS
• Interrupt Control Unit (ICU)
  • 9.1 FEATURES
  • 9.2 FUNCTIONAL DESCRIPTION
    • 9.2.1 NMI
    • 9.2.2 Maskable Interrupts
    • 9.2.3 Edge/Level and Polarity Selection
    • 9.2.4 Pending Interrupts
    • 9.2.5 External Interrupt Inputs
    • 9.2.6 Interrupt Assignment
  • 9.3 ICU REGISTERS
    • 9.3.1 NMI Status Register (NMISTAT)
    • 9.3.2 Power Fail Control Register (PFAIL)
    • 9.3.3 Interrupt Vector Register (IVCT)
    • 9.3.4 Interrupt Enable and Mask Register (IENAM)
    • 9.3.5 Interrupt Pending Register (IPEND)
    • 9.3.6 Edge Interrupt Clear Register (IECLR)
    • 9.3.7 Edge/Level Trigger Configuration Register (I...
    • 9.3.8 Trigger Polarity Configuration Register (ITR...
  • 9.4 USAGE HINTS
    • 9.4.1 Initializing
    • 9.4.2 Clearing
    • 9.4.3 Nesting
• Multi-Input Wake-Up (MIWU)
  • 10.1 FEATURES
  • 10.2 FUNCTIONAL DESCRIPTION
    • 10.2.1 Trigger Conditions
    • 10.2.2 Pending Flags
    • 10.2.3 Input Enable
    • 10.2.4 Interrupts
    • 10.2.5 Input Assignments
  • 10.3 MIWU REGISTERS
    • 10.3.1 Edge Detection Register 1(WKEDG1)
    • 10.3.2 Edge Detection Register 2 (WKEDG2)
    • 10.3.3 Edge Detection Register 3 (WKEDG3)
    • 10.3.4 Pending Register 1 (WKPND1)
    • 10.3.5 Pending Register 2 (WKPND2)
    • 10.3.6 Pending Register 3 (WKPND3)
    • 10.3.7 Wake-Up Enable Register 1 (WKEN1)
    • 10.3.8 Wake-Up Enable Register 2 (WKEN2)
    • 10.3.9 Wake-Up Enable Register 3 (WKEN3)
    • 10.3.10 Pending Clear Register 1 (WKPCL1)
    • 10.3.11 Pending Clear Register 2 (WKPCL2)
    • 10.3.12 Pending Clear Register 3 (WKPCL3)
  • 10.4 USAGE HINTS
• General Purpose I/O (GPIO) Ports
  • 11.1 FEATURES
  • 11.2 FUNCTIONAL DESCRIPTION
    • 11.2.1 Output Buffer
    • 11.2.2 Input Buffer
    • 11.2.3 Open Drain
    • 11.2.4 Weak Pull-Up
  • 11.3 GPIO PORT REGISTERS
    • 11.3.1 Port Alternate Function Register (PxALT)
    • 11.3.2 Port Direction Register (PxDIR)
    • 11.3.3 Port Data Out Register (PxDOUT)
    • 11.3.4 Port Data In Register (PxDIN)
    • 11.3.5 Port Weak Pull-up Register (PxWPU)
• PS/2 Interface
  • 12.1 FEATURES
  • 12.2 FUNCTIONAL DESCRIPTION
    • 12.2.1 Configuration
    • 12.2.2 Shift Mechanism
    • 12.2.3 Quasi-Bidirectional Drivers
    • 12.2.4 Interrupt Signals
    • 12.2.5 Power Modes
  • 12.3 SHIFT MECHANISM ENABLED
    • 12.3.1 Reset
    • 12.3.2 Enable
    • 12.3.3 General PS/2 Interface Operation
    • 12.3.4 Transmit Mode
  • 12.4 SHIFT MECHANISM DISABLED
    • 12.4.1 Clock Signal Control
    • 12.4.2 Data Signal Control
    • 12.4.3 Interrupt Generation
  • 12.5 PS/2 INTERFACE REGISTERS
    • 12.5.1 PS/2 Data Register (PSDAT)
    • 12.5.2 PS/2 Status Register (PSTAT)
    • 12.5.3 PS/2 Control Register (PSCON)
    • 12.5.4 PS/2 Output Signal Register (PSOSIG)
    • 12.5.5 PS/2 Input Signal Register (PSISIG)
    • 12.5.6 PS/2 Interrupt Enable Register (PSIEN)
• ACCESS.bus (ACB) Interface
  • 13.1 FEATURES
  • 13.2 ACB PROTOCOL OVERVIEW
    • 13.2.1 ACB Interface
    • 13.2.2 Data Transactions
    • 13.2.3 Start and Stop
    • 13.2.4 Acknowledge Cycle
    • 13.2.5 �Acknowledge after every byte� Rule
    • 13.2.6 Addressing Transfer Formats
    • 13.2.7 Arbitration on the Bus
  • 13.3 FUNCTIONAL DESCRIPTION
    • 13.3.1 Master Mode
    • 13.3.2 Slave Mode
    • 13.3.3 Power-Down
    • 13.3.4 SDA and SCL Pin Configuration
    • 13.3.5 ACB Clock Frequency Configuration
  • 13.4 ACB REGISTERS
    • 13.4.1 ACB Serial Data Register (ACBSDA)
    • 13.4.2 ACB Status Register (ACBST)
    • 13.4.3 ACB Control Status Register (ACBCST)
    • 13.4.4 ACB Control Register 1 (ACBCTL)
    • 13.4.5 ACB Own Address Register (ACBADDR)
    • 13.4.6 ACB Control Register 2 (ACBCTL2)
  • 13.5 USAGE HINTS
• Multi-Function 16-Bit Timer (MFT16)
  • 14.1 FEATURES
  • 14.2 FUNCTIONAL DESCRIPTION
  • 14.3 CLOCK SOURCE UNIT
    • 14.3.1 Prescaler
    • 14.3.2 External Event Clock
    • 14.3.3 Pulse Accumulate Mode
    • 14.3.4 Slow Speed Clock
    • 14.3.5 Counter Clock Source Select
  • 14.4 TIMER/COUNTER AND ACTION UNIT
    • 14.4.1 Operation Modes
    • 14.4.2 Timer Interrupts
    • 14.4.3 Timer I/O Functions
  • 14.5 MFT16 REGISTERS
    • 14.5.1 Clock Prescaler Register (TPRSC)
    • 14.5.2 Clock Unit Control Register (TCKC)
    • 14.5.3 Timer/Counter Register 1 (TCNT1)
    • 14.5.4 Timer/Counter Register 2 (TCNT2)
    • 14.5.5 Reload/Capture Register A(TCRA)
    • 14.5.6 Reload/Capture Register B (TCRB)
    • 14.5.7 Timer Mode Control Register (TCTRL)
    • 14.5.8 Timer Interrupt Control Register (TICTL)
    • 14.5.9 Timer Interrupt Clear Register (TICLR)
• Timer and WATCHDOG (TWD)
  • 15.1 FEATURES
  • 15.2 FUNCTIONAL Description
    • 15.2.1 Input Clock
    • 15.2.2 Pre-Scale
    • 15.2.3 TWD Timer 0
  • 15.3 WATCHDOG OPERATION
  • 15.4 TWD CONTROL AND CONFIGURATION
  • 15.5 OPERATION IN IDLE MODE
  • 15.6 TWD REGISTERS
    • 15.6.1 Timer and WATCHDOG Configuration Registers ...
    • 15.6.2 Timer and Watchdog Clock Pre-Scaler Registe...
    • 15.6.3 TWD Timer 0 Register (TWDT0)
    • 15.6.4 TWDT0 Control and Status Register (T0CSR)
    • 15.6.5 WATCHDOG Count Register (WDCNT)
    • 15.6.6 WATCHDOG Service Data Match Register (WDSDM...
  • 15.7 USAGE HINTS
• Analog to Digital Converter (ADC)
  • 16.1 FEATURES
  • 16.2 FUNCTIONAL DESCRIPTION
    • 16.2.1 Reset
    • 16.2.2 Reference Voltage
    • 16.2.3 Input Signal Range
    • 16.2.4 ADC Clock
    • 16.2.5 Initializing and Enabling the ADC
    • 16.2.6 ADC Operation
    • 16.2.7 Disabling the ADC to Save Power
    • 16.2.8 Sampling Time
    • 16.2.9 Polling Driven Operation
    • 16.2.10 Interrupt Driven Operation
    • 16.2.11 Overflow
  • 16.3 OPERATION MODES
  • 16.4 ADC REGISTERS
    • 16.4.1 ADC Status Register (ADCST)
    • 16.4.2 ADC Control Register 1 (ADCCNT1)
    • 16.4.3 ADC Control Register 2 (ADCCNT2)
    • 16.4.4 ADC Control Register 3 (ADCCNT3)
    • 16.4.5 ADC Data Registers
  • 16.5 USAGE HINTS
    • 16.5.1 Power Supply and Layout Guidelines
    • 16.5.2 Power Consumption
    • 16.5.3 Filtering the Noise on Input Signals
    • 16.5.4 AD0-7 Multiplexing with PD0-7 Port
    • 16.5.5 Calculating the Sampling Time
• Digital to Analog Converter (DAC)
  • 17.1 FEATURES
  • 17.2 FUNCTIONAL DESCRIPTION
    • 17.2.1 DAC Reset
    • 17.2.2 Reference Voltage
    • 17.2.3 Output Signal Range
    • 17.2.4 Initializing and Enabling the DAC
    • 17.2.5 Disabling the DAC
    • 17.2.6 Conversion Start
  • 17.3 DAC REGISTERS
    • 17.3.1 DAC Control Register (DACCTRL)
    • 17.3.2 DAC Data Registers
  • 17.4 USAGE HINTS
    • 17.4.1 Power Supply and Layout Guidelines
    • 17.4.2 Output Settling Time
    • 17.4.3 Output Voltage Accuracy
    • 17.4.4 Filtering Noise on Output Signals
    • 17.4.5 Current Consumption
    • 17.4.6 Entering Idle Mode
• Development System Support
  • 18.1 ISE INTERRUPT
  • 18.2 TRIS STRAP INPUT PIN
  • 18.3 FREEZING EVENTS
    • 18.3.1 Disabling Maskable Interrupts
    • 18.3.2 Freezing the WATCHDOG Counter
    • 18.3.3 Disabling Additional Modules
    • 18.3.4 Disabling Destructive Reads
  • 18.4 MONITORING ACTIVITY DURING DEVELOPMENT
    • 18.4.1 The Bus Status Signals
    • 18.4.2 Transaction Effects on the External Bus
    • 18.4.3 Pipe Status Signals
  • 18.5 DEVELOPMENT SYSTEM REGISTERS
    • 18.5.1 Debug Configuration Register (DBGCFG)
    • 18.5.2 Debug Freeze Enable Register (DBGFRZEN)
• Device Specifications
  • 19.1 POWER AND GROUNDING
  • 19.2 GENERAL DC ELECTRICAL CHARACTERISTICS
    • 19.2.1 Recommended Operating Conditions
    • 19.2.2 Absolute Maximum Ratings
    • 19.2.3 Power Supply Current under Recommended Oper...
  • 19.3 DC ELECTRICAL CHARACTERISTICS
    • 19.3.1 Analog
    • 19.3.2 Digital
  • 19.4 AC ELECTRICAL CHARACTERISTICS
    • 19.4.1 Definitions
    • 19.4.2 Timing Tables
  • 19.5 TIMING DIAGRAMS
    • 19.5.1 General
    • 19.5.2 BIU
    • 19.5.3 GPIO Ports
    • 19.5.4 Host Interface
    • 19.5.5 MFT16
    • 19.5.6 ACCESS Bus Interface
    • 19.5.7 Dev Environment Support
    • 19.5.8 Interrupts and Wake-up
    • 19.5.9 Reset
    • 19.5.10 Host Power-on
    • 19.5.11 PS/2 Interface
• CR16A Register Map
• Bootloader Description
  • B.1 OVERVIEW
  • B.2 CONFIGURATION BLOCKS
    • B.2.1 System Configuration Block
    • B.2.2 KBC Header
  • B.3 SYSTEM RESOURCES USED BY BOOTLOADER
    • B.3.1 GPIO Pins
    • B.3.2 On-Chip RAM
  • B.4 BOOTLOADER PROGRAM OPERATION