TL C 12379

PC87306

SuperIO

Enhanced

Sidewinder

Lite

Floppy

Disk

Controller

Keyboard

Controller

Real-Time

Clock

Dual

UARTs

Infrared

Interface

IEEE

1284

Parallel

Port

and

IDE

Interface

PRELIMINARY

November 1995

PC87306 SuperI O

Enhanced Sidewinder Lite

Floppy Disk Controller Keyboard Controller
Real-Time Clock Dual UARTs Infrared Interface
IEEE 1284 Parallel Port and IDE Interface

General Description

The PC87306 is a single chip solution incorporating a Key-
board and PS 2

Mouse Controller (KBC) Real Time Clock

(RTC) and most commonly used I O peripherals in ISA
EISA and MicroChannel

based computers In addition to

the KBC and RTC a Floppy Disk Controller (FDC) two full
featured UARTs an IEEE 1284 compatible parallel port and
all the necessary control logic for an IDE interface provides
support for most commonly used I O peripherals Standard
PC-AT

address decoding for all the peripherals a set of

configuration registers and two user selectable chip selects
are also implemented in this highly integrated member of
the SuperI O family The advanced features and high inte-
gration of the PC87306 result in several benefits for low
cost high performance systems Printed circuit board space
savings fewer components on the motherboard and com-
patibility with the latest industry standard peripherals are
only a few of the benefits of using a PC87306

The KBC is fully software compatible with the 8042AH mi-
crocontroller It contains system timing control logic cus-
tom ROM program memory RAM data memory and 18 pro-
grammable I O lines necessary to implement dedicated
control functions It is an efficient controller which uses pre-
dominantly single byte instructions with support for binary and
BCD arithmetic and extensive bit handling capabilities

(Continued)

Features

Floppy Disk Controller

Software compatible with the DP8477 the 765A and
the N82077
16-byte FIFO (disabled by default)
Burst and Non-Burst modes
Perpendicular recording drive support
High performance internal analog data separator
(no external filter components required)
Low power CMOS with power-down mode
Automatic media-sense support with full IBM TDR
(Tape Drive Register) implementation for PC-AT and
PS 2 floppy drive types

Keyboard Controller

8042AH and PC87911 software compatible
8-bit Microcomputer with 2 kBytes custom ROM and
256 Bytes data RAM
Asynchronous access to two data registers and one
status register during normal operation
Dedicated open drain outputs for keyboard controller
application
Supports both interrupt and polling
10 programmable I O pins
4 dedicated open-drain bidirectional pins
8-bit Timer Counter
Binary and BCD arithmetic

(Continued)

Block Diagram

TL C 12379 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

SuperI O

is a trademark of National Semiconductor Corporation

MicroChannel

PC-AT

and PS 2

are registered trademarks of International Business Machines Corporation

C1995 National Semiconductor Corporation

RRD-B30M115 Printed in U S A

General Description

(Continued)

The RTC is a low-power design that provides a time-of-day
clock a 100-year calendar several alarm features and 242
bytes of general purpose RAM An external battery is used
to maintain the time and contents of the general purpose
RAM when power is removed from the PC87306 The
PC87306 RTC is compatible with the DS1287 and
MC146818 RTC devices

The PC87306 FDC uses a high performance analog data
separator eliminating need for any external filter compo-
nents The FDC is fully compatible with the PC8477 and
incorporates a superset of DP8473 NEC mPD765 and
N82077 floppy disk controller function All popular 5 25
and 3 5 floppy drives including 2 88 MB 3 5 floppy drive
are supported Full TDR support for PC-AT and PS 2 floppy
drive types is also provided

The two UARTs are fully NS16450 and NS16550 compati-
ble

The parallel port is fully IEEE 1284 level 2 compatible The
SPP (Standard Parallel Port) is fully compatible with ISA
EISA and MicroChannel parallel ports In addition to the
SPP EPP (Enhanced Parallel Port) and ECP (Extended Ca-
pabilities Port) modes are supported by the parallel port

All IDE control signals with DMA support including support
for Type F DMA are provided by the PC87306 Only external
signal buffers are required to implement a complete IDE
interface

A set of fourteen configuration registers are provided to
control various functions of the PC87306 These registers
are accessed using two 8-bit wide index and data registers
The ISA I O address of the register pair can be relocated
using a power-up strapping option

Two general purpose user programmable chip selects are
available These chip selects can be used to decode game
port addresses

Features

(Continued)

Real-Time Clock

DS1287 MC146818 and PC87911 compatible
242 Bytes battery backed-up CMOS RAM in two
banks
Selective lock mechanism locks any half of the RTC
RAM
Calendar in days

day of the week

months and

years with automatic leap-year adjustment
Time of day in seconds minutes and hours

12 or 24 hour format

Optional daylight savings adjustment

BCD or binary format for time keeping
Three individually maskable interrupt event flags

Periodic rates from 122 ms to 500 ms
Time-of-day alarm once per second to once per
day

Separate battery pin 2 4V operation
2 mA typical power consumption
Double buffer time registers

UARTs

Software compatible with the PC16550A and
NS16450
IrDA Infrared and HP SIR Interface using UART2
with dedicated pins

Parallel Port

EPP ECP compatible with ECP level 2 support
Bi-directional data transfer under software or
hardware control
Includes protection circuit to prevent damage to the
parallel port when a connected printer is powered up
or is operated at a higher voltage

IDE Control Logic

All IDE control signals with DMA and support for
Type F DMA Only external signal buffers are
required to implement the full IDE interface

General Purpose Pins

Separate pins for two user programmable chip select
decoders provide ability to control a game port
16 additional general purpose I O ports

Address Decoder

Provides selection of all primary and secondary ISA
addresses including COM1 4

Plug and Play

Flexible IRQs and DMAs to meet the Plug and Play
requirements of Microsoft's PC '95 Hardware Design
Guide
Multi-programmable parallel port base address

General

ISA EISA and MicroChannel compatible architecture
Low power CMOS technology
Ability to stop clocks to all modules
The PC87323 which includes RAM KBC can be
used as a development platform for KBC code for
the PC87306
Reduced pin leakage current
Special configuration register for power-down
Disable bit for RTC
160-pin PQFP package

Table of Contents

1 0 PIN DESCRIPTION

2 0 CONFIGURATION REGISTERS

2 1 Overview

2 2 Software Configuration

2 3 Hardware Configuration

2 4 Index and Data Registers

2 5 Base Configuration Registers

2 5 1 Function Enable Register

2 5 2 Function Address Register

2 5 3 Power and Test Register

2 5 4 Function Control Register

2 5 5 Printer Control Register

2 5 6 KBC and RTC Control Register

2 5 7 Power Management Control Register

2 5 8 Tape UARTs and Parallel Port Configuration

2 5 9 SuperI O Identification Register

2 5 10 Advanced SuperI O Configuration Register

2 5 11 Chip Select 0 Low Address

2 5 12 Chip Select 0 High Address

2 5 13 Chip Select 0 Configuration Register

2 5 14 Chip Select 1 Low Address

2 5 15 Chip Select 1 High Address

2 5 16 Chip Select 1 Configuration Register

2 5 17 InfraRed Configuration Register

2 5 18 General Purpose I O Port Base Address

Configuration Register

2 5 19 SuperI O Configuration Register 0

2 5 20 SuperI O Configuration Register 1

2 5 21 LPT Base Address Register

2 5 22 Plug and Play Configuration 0 Register

2 5 23 Plug and Play Configuration 1 Register

2 6 Power-Down Options

2 7 Power-Up Procedure and Considerations

2 7 1 UART Power-Up

2 7 2 FDC Power-Up

3 0 FDC REGISTER DESCRIPTION

3 1 FDC Control Registers

3 1 1 Status Register A (SRA) Read Only

3 1 2 Status Register B (SRB) Read Only

3 1 3 Digital Output Register (DOR) Read Write

3 1 4 Tape Drive Register (TDR) Read Write

3 1 5 Main Status Register (MSR) Read Only

3 1 6 Data Rate Select Register (DSR) Write Only

3 1 7 Data Register (FIFO) Read Write

3 1 8 Digital Input Register (DIR) Read Only

3 1 9 Configuration Control Register (CCR)

Write Only

3 2 Result Phase Status Registers

3 2 1 Status Register 0 (ST0)

3 2 2 Status Register 1 (ST1)

3 0 FDC REGISTER DESCRIPTION

(Continued)

3 2 3 Status Register 2 (ST2)

3 2 4 Status Register 3 (ST3)

4 0 FDC COMMAND SET DESCRIPTION

4 1 Command Descriptions

4 1 1 Configure Command

4 1 2 Dumpreg Command

4 1 3 Format Track Command

4 1 4 Invalid Command

4 1 5 Lock Command

4 1 6 Mode Command

4 1 7 NSC Command

4 1 8 Perpendicular Mode Command

4 1 9 Read Data Command

4 1 10 Read Deleted Data Command

4 1 11 Read ID Command

4 1 12 Read A Track Command

4 1 13 Recalibrate Command

4 1 14 Relative Seek Command

4 1 15 Scan Commands

4 1 16 Seek Command

4 1 17 Sense Drive Status Command

4 1 18 Sense Interrupt Command

4 1 19 Set Track Command

4 1 20 Specify Command

4 1 21 Verify Command

4 1 22 Version Command

4 1 23 Write Data Command

4 1 24 Write Deleted Data Command

4 2 Command Set Summary

4 3 Mnemonic Definitions for FDC Commands

5 0 FDC FUNCTIONAL DESCRIPTION

5 1 Microprocessor Interface

5 2 Modes of Operation

5 3 Controller Phases

5 3 1 Command Phase

5 3 2 Execution Phase

5 3 2 1 DMA Mode

FIFO Disabled

5 3 2 2 DMA Mode

FIFO Enabled

5 3 2 3 Interrupt Mode

FIFO Disabled

5 3 2 4 Interrupt Mode

FIFO Enabled

5 3 2 5 Software Polling

5 3 3 Result Phase

5 3 4 Idle Phase

5 3 5 Drive Polling Phase

5 4 Data Separator

5 5 Crystal Oscillator

5 6 Perpendicular Recording Mode

5 7 Data Rate Selection

5 8 Write Precompensation

Table of Contents

(Continued)

5 0 FDC FUNCTIONAL DESCRIPTION

(Continued)

5 9 FDC Low Power Mode Logic

5 10 Reset Operation

6 0 SERIAL PORTS

6 1 Serial Port Registers

6 2 Line Control Register (LCR) Read Write

6 3 Programmable Baud Rate Generator

6 4 Line Status Register (LSR)

6 5 FIFO Control Register (FCR)

6 6 Interrupt Identification Register (IIR)

6 7 Interrupt Enable Register (IER)

6 8 MODEM Control Register (MCR)

6 9 MODEM Status Register (MSR)

6 10 Scratchpad Register (SCR)

7 0 SERIAL INFRARED WIRELESS COMMUNICATION

PORT

8 0 PARALLEL PORT

8 1 Introduction

8 2 Data Register (DTR)

8 3 Status Register (STR)

8 4 Control Register (CTR)

8 5 Enhanced Parallel Port Operation

8 6 Extended Capabilities Parallel Port (ECP)

8 6 1 Introduction

8 6 2 Software Operation

8 7 Register Definitions

8 8 Software Controlled Data Transfer

8 9 Automatic Data Transfer

8 9 1 Forward Direction

8 9 2 ECP Forward Write Cycle

8 9 3 Backward Direction

8 9 4 ECP Backward Read Cycle

8 10 FIFO Test Access

8 11 Configuration Registers Access

8 12 Interrupt Generation

9 0 INTEGRATED DEVICE ELECTRONICS INTERFACE

(IDE)

9 1 Introduction

9 2 IDE Signals

10 0 KEYBOARD CONTROLLER AND REAL-TIME

CLOCK

10 1 PC87306 KBC Function

10 1 1 Host System Interface

10 1 2 Program Memory

10 1 3 Data Memory and Registers

10 1 4 I O Interface

10 1 5 Timer Counter

10 0 KEYBOARD CONTROLLER AND REAL-TIME

CLOCK

(Continued)

10 1 6 Interrupts

10 1 7 Oscillator and Instruction Timing

10 2 Real-Time Clock Function

10 2 1 Memory Map

10 2 2 Bus Interface

10 2 3 Time Generation

10 2 4 Time Keeping

10 2 5 RAM

10 2 6 Power Management

10 2 7 System Bus Lock Out and Power-Up

Detection

10 2 8 Oscillator

10 2 9 Interrupt Handling

10 2 10 Control Registers

11 0 GENERAL PURPOSE INPUT AND OUTPUT (GPIO)

PORTS

12 0 ELECTRICAL CHARACTERISTICS

12 1 DC Electrical Characteristics

12 1 1 Microprocessor Parallel Port and

IDE Interface Pins

12 1 2 Disk Interface Pins

12 1 3 Oscillator Pin

12 1 4 Parallel Port Pins

12 1 5 GPIO Pins

12 1 6 Keyboard Controller and Real-Time Clock

Pins

12 2 AC Electrical Characteristics

12 2 1 AC Test Conditions

12 2 2 Clock Timing

12 2 3 Microprocessor Interface Timing

12 2 4 Baud Out Timing

12 2 5 Transmitter Timing

12 2 6 Receiver Timing

12 2 7 MODEM Control Timing

12 2 8 DMA Timing

12 2 8 1 FDC

12 2 8 2 ECP

12 2 9 Reset Timing

12 2 10 FDC Write Data Timing

12 2 11 FDC Read Data Timing

12 2 12 Drive Control Timing

12 2 13 IDE Timing

12 2 14 Parallel Port Timing

12 2 15 Enhanced Parallel Port Timing

12 2 16 Extended Capabilities Port Timing

12 2 16 1 Forward

12 2 16 2 Backward

12 2 17 GPIO Write Timing

12 2 18 RTC

12 2 19 Programmable Chip Select Timing

List of Figures

FIGURE 1-1

Pins Which Utilize the Strap Function during Reset

FIGURE 1-2

Multi-Function Pins

FIGURE 2-1

PC87306 Configuration Registers

FIGURE 2-2

PC87306 Four Floppy Drive Circuit

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

FDC Command Structure

FIGURE 4-2

IBM Perpendicular and ISO Formats Supported by the Format Command

FIGURE 5-1

FDC Data Separator Block Diagram

FIGURE 5-2

PC87306 Dynamic Window Margin Performance

FIGURE 5-3

Read Data Algorithm

State Diagram

FIGURE 5-4

Perpendicular Recording Drive R W Head and Pre-Erase Head

FIGURE 6-1

PC87306 Composite Serial Data

FIGURE 6-2

Receiver FIFO Trigger Level

FIGURE 7-1

UART2 Serial and IR Interface Block Diagram

FIGURE 8-1

EPP 1 7 Address Write

FIGURE 8-2

EPP 1 7 Address Read

FIGURE 8-3

EPP Write with ZWS

FIGURE 8-4

EPP 1 9 Address Write

FIGURE 8-5

EPP 1 9 Address Read

FIGURE 8-6

ECP Forward Write Cycle

FIGURE 8-7

ECP Backward Read Cycle

FIGURE 9-1

IDE Interface Signal Equations (Non-DMA)

FIGURE 10-1

Keyboard Controller Functional Block Diagram

FIGURE 10-2

Keyboard Controller to Host System Interface

FIGURE 10-3

Status Register

FIGURE 10-4

Fast IRQ Latching and Clearing

FIGURE 10-5

Keyboard Controller Data Memory Map

FIGURE 10-7

PSW Register Bits

FIGURE 10-6

Keyboard Controller Stack Organization

FIGURE 10-8

Active Pull-Up I O Port Structure

FIGURE 10-9

Using Port Pins as Inputs

FIGURE 10-10

Timing Generation and Timer Circuit

FIGURE 10-11

External Clock Connection

FIGURE 10-12

Instruction Cycle Timing

FIGURE 10-13

Oscillator Internal and External Circuitry

FIGURE 10-14

Interrupt Status Timing

FIGURE 10-15

Typical Battery Configuration

FIGURE 10-16

Typical Battery Current during Battery Backed Mode

FIGURE 11-1

General Purpose I O (GPIO) Ports

FIGURE 12-1

Clock Timing

FIGURE 12-2

Microprocessor Read Timing

FIGURE 12-3

Microprocessor Write Timing

FIGURE 12-4

Read after Write Operation to All Registers and RAM Timing

FIGURE 12-5

Baud Out Timing

FIGURE 12-6

Transmitter Timing

FIGURE 12-7

Receiver Timing

FIGURE 12-8

FIFO Mode Receiver Timing

FIGURE 12-9

Timeout Receiver Timing

FIGURE 12-10

MODEM Control Timing

FIGURE 12-11

FDC DMA Timing

FIGURE 12-12

ECP DMA Timing

FIGURE 12-13

Reset Timing

FIGURE 12-14

Write Data Timing

Part Number PC87306