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Part Number MM74C374

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TL F 5906
MM54C373MM74C373
TRI-STATE
Octal
D-Type
Latch
MM54C374MM74C374
TRI-STATE
Octal
D-Type
Flip-Flop
March 1988
MM54C373 MM74C373 TRI-STATE
Octal D-Type Latch
MM54C374 MM74C374 TRI-STATE Octal D-Type Flip-Flop
General Description
The MM54C373 MM74C373 MM54C374 MM74C374 are
integrated complementary MOS (CMOS) 8-bit storage ele-
ments with TRI-STATE outputs These outputs have been
specially designed to drive high capacitive loads such as
one might find when driving a bus and to have a fan out of 1
when driving standard TTL When a high logic level is ap-
plied to the OUTPUT DISABLE input all outputs go to a high
impedance state regardless of what signals are present at
the other inputs and the state of the storage elements
The MM54C373 MM74C373 is an 8-bit latch When LATCH
ENABLE is high the Q outputs will follow the D inputs
When LATCH ENABLE goes low data at the D inputs
which meets the set-up and hold time requirements will be
retained at the outputs until LATCH ENABLE returns high
again
The MM54C374 MM74C374 is an 8-bit D-type positive-
edge triggered flip-flop Data at the D inputs meeting the
set-up and hold time requirements is transferred to the Q
outputs on positive-going transitions of the CLOCK input
Both the MM54C373 MM74C373 and the MM54C374
MM74C374 are being assembled in 20-pin dual-in-line pack-
ages with 0 300
pin centers
Features
Y
Wide supply voltage range
3V to 15V
Y
High noise immunity
0 45 V
CC
(typ )
Y
Low power consumption
Y
TTL compatibility
Fan out of 1
driving standard TTL
Y
Bus driving capability
Y
TRI-STATE outputs
Y
Eight storage elements in one package
Y
Single CLOCK LATCH ENABLE and OUTPUT
DISABLE control inputs
Y
20-pin dual-in-line package with 0 300
centers takes
half the board space of a 24-pin package
Connection Diagrams
MM54C373 MM74C373
Dual-In-Line Package
TL F 5906 ­ 1
Top View
Order Number MM54C373 or MM74C373
MM54C374 MM74C374
Dual-In-Line Package
TL F 5906 ­ 2
Top View
Order Number MM54C374 or MM74C374
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
b
0 3V to V
CC
a
0 3V
Operating Temperature Range (T
A
)
MM54C373
b
55 C to
a
125 C
MM74C373
b
40 C to
a
85 C
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation
Dual-In-Line
700 mW
Small Outline
500 mW
Operating V
CC
Range
3V to 15V
Absolute Maximum V
CC
18V
Lead Temperature (T
L
)
(Soldering 10 seconds)
260 C
DC Electrical Characteristics
Min Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical ``1'' Input Voltage
V
CC
e
5V
3 5
V
V
CC
e
10V
8 0
V
V
IN(0)
Logical ``0'' Input Voltage
V
CC
e
5V
1 5
V
V
CC
e
10V
2 0
V
V
OUT(1)
Logical ``1'' Output Voltage
V
CC
e
5V I
O
e b
10 mA
4 5
V
V
CC
e
10V I
O
e b
10 mA
9 0
V
V
OUT(0)
Logical ``0'' Output Voltage
V
CC
e
5V I
O
e
10 mA
0 5
V
V
CC
e
10V I
O
e
10 mA
1 0
V
I
IN(1)
Logical ``1'' Input Current
V
CC
e
15V V
IN
e
15V
0 005
1 0
m
A
I
IN(0)
Logical ``0'' Input Current
V
CC
e
15V V
IN
e
0V
b
1 0
b
0 005
m
A
I
OZ
TRI-STATE Leakage Current
V
CC
e
15V V
O
e
15V
0 005
1 0
m
A
V
CC
e
15V V
O
e
0V
b
1 0
b
0 005
m
A
I
CC
Supply Current
V
CC
e
15V
0 05
300
m
A
CMOS LPTTL INTERFACE
V
IN(1)
Logical ``1'' Input Voltage
54C
V
CC
e
4 5V
V
CC
b
1 5
V
74C
V
CC
e
4 75V
V
CC
b
1 5
V
V
IN(0)
Logical ``0'' Input Voltage
54C
V
CC
e
4 5V
0 8
V
54C
V
CC
e
4 75V
0 8
V
V
OUT(1)
Logical ``1'' Output Voltage
54C
V
CC
e
4 5V I
O
e b
360 mA
V
CC
b
0 4
V
74C
V
CC
e
4 75V I
O
e b
360 mA
V
CC
b
0 4
V
54C
V
CC
e
4 5V I
O
e b
1 6 mA
2 4
V
74C
V
CC
e
4 75V I
O
e b
1 6 mA
2 4
V
V
OUT(0)
Logical ``0'' Output Voltage
54C
V
CC
e
4 5V I
O
e
1 6 mA
0 4
V
74C
V
CC
e
4 75V I
O
e
1 6 mA
0 4
V
OUTPUT DRIVE (Short Circuit Current)
I
SOURCE
Output Source Current
V
CC
e
5V V
OUT
e
0V
b
12
b
24
mA
T
A
e
25 C (Note 4)
I
SOURCE
Output Source Current
V
CC
e
10V V
OUT
e
0V
b
24
b
48
mA
T
A
e
25 C (Note 4)
I
SINK
Output Sink Current
V
CC
e
5V V
OUT
e
V
CC
6
12
mA
(N-Channel)
T
A
e
25 C (Note 4)
I
SINK
Output Sink Current
V
CC
e
10V V
OUT
e
V
CC
24
48
mA
(N-Channel)
T
A
e
25 C (Note 4)
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
2
AC Electrical Characteristics
MM54C373 MM74C373 T
A
e
25 C C
L
e
50 pF t
r
e
t
f
e
20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd0
t
pd1
Propagation Delay
V
CC
e
5V C
L
e
50 pF
165
330
ns
LATCH ENABLE to Output
V
CC
e
10V C
L
e
50 pF
70
140
ns
V
CC
e
5V C
L
e
150 pF
195
390
ns
V
CC
e
10V C
L
e
150 pF
85
170
ns
t
pd0
t
pd1
Propagation Delay Data
LATCH ENABLE
e
V
CC
In to Output
V
CC
e
5V C
L
e
50 pF
155
310
ns
V
CC
e
10V C
L
e
50 pF
70
140
ns
V
CC
e
5V C
L
e
150 pF
185
370
ns
V
CC
e
10V C
L
e
150 pF
85
170
ns
t
SET-UP
Minimum Set-Up Time Data In
t
HOLD
e
0 ns
to CLOCK LATCH ENABLE
V
CC
e
5V
70
140
ns
V
CC
e
10V
35
70
ns
f
MAX
Maximum LATCH ENABLE
Frequency
V
CC
e
5V
3 5
6 7
MHz
V
CC
e
10V
4 5
9 0
MHz
t
PWH
Minimum LATCH ENABLE
V
CC
5V
75
150
ns
Pulse Width
V
CC
e
10V
55
110
ns
t
r
t
f
Maximum LATCH ENABLE
V
CC
e
5V
NA
m
s
Rise and Fall Time
V
CC
e
10V
NA
m
s
t
1H
t
0H
Propagation Delay OUTPUT
R
L
e
10k C
L
e
5 pF
DISABLE to High Impedance
V
CC
e
5V
105
210
ns
State (from a Logic Level)
V
CC
e
10V
60
120
ns
t
H1
t
H0
Propagation Delay OUTPUT
R
L
e
10k C
L
e
50 pF
DISABLE to Logic Level
V
CC
e
5V
105
210
ns
(from High Impedance State)
V
CC
e
10V
45
90
ns
t
THL
t
TLH
Transition Time
V
CC
e
5V C
L
e
50 pF
65
130
ns
V
CC
e
10V C
L
e
50 pF
35
70
ns
V
CC
e
5V C
L
e
150 pF
110
220
ns
V
CC
e
10V C
L
e
150 pF
70
140
ns
C
LE
Input Capacitance
LE Input (Note 2)
7 5
10
pF
C
OD
Input Capacitance
OUTPUT DISABLE
7 5
10
pF
Input (Note 2)
C
IN
Input Capacitance
Any Other Input (Note 2)
5
7 5
pF
C
OUT
Output Capacitance
High Impedance
10
15
pF
State (Note 2)
C
PD
Power Dissipation Capacitance
Per Package (Note 3)
200
pF
AC Parameters are guaranteed by DC correlated testing
3
AC Electrical Characteristics
(Continued)
MM54C374 MM74C374 T
A
e
25 C C
L
e
50 pF t
r
e
t
f
e
20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd0
t
pd1
Propagation Delay
V
CC
e
5V C
L
e
50 pF
150
300
ns
CLOCK to Output
V
CC
e
10V C
L
e
50 pF
65
130
ns
V
CC
e
5V C
L
e
150 pF
180
360
ns
V
CC
e
10V C
L
e
150 pF
80
160
ns
t
SET-UP
Minimum Set-Up Time Data In
t
HOLD
e
0 ns
to CLOCK LATCH ENABLE
V
CC
e
5V
70
140
ns
V
CC
e
10V
35
70
ns
t
PWH
t
PWL
Minimum CLOCK Pulse Width
V
CC
e
5V
70
140
ns
V
CC
e
10V
50
100
ns
f
MAX
Maximum CLOCK Frequency
V
CC
e
5V
3 5
7 0
MHz
V
CC
e
10V
5
10
MHz
t
1H
t
0H
Propagation Delay OUTPUT
R
L
e
10k C
L
e
50 pF
DISABLE to High Impedance
V
CC
e
5V
105
210
ns
State (from a Logic Level)
V
CC
e
10V
60
120
ns
t
H1
t
H0
Propagation Delay OUTPUT
R
L
e
10k C
L
e
50 pF
DISABLE to Logic Level
V
CC
e
5V
105
210
ns
(from High Impedance State)
V
CC
e
10V
45
90
ns
t
THL
t
TLH
Transition Time
V
CC
e
5V C
L
e
50 pF
65
130
ns
V
CC
e
10V C
L
e
50 pF
35
70
ns
V
CC
e
5V C
L
e
150 pF
110
220
ns
V
CC
e
10V C
L
e
150 pF
70
140
ns
t
r
t
f
Maximum CLOCK Rise
V
CC
e
5V
15
l
2000
m
s
and Fall Time
V
CC
e
10V
5
l
2000
m
s
C
CLK
Input Capacitance
CLOCK Input (Note 2)
7 5
10
pF
C
OD
Input Capacitance
OUTPUT DISABLE
7 5
10
pF
Input (Note 2)
C
IN
Input Capacitance
Any Other Input (Note 2)
5
7 5
pF
C
OUT
Output Capacitance
High Impedance
10
15
pF
State (Note 2)
C
PD
Power Dissipation Capacitance
Per Package (Note 3)
250
pF
AC Parameters are guaranteed by DC correlated testing
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note
AN-90
Note 4
These are peak output current capabilities Continuous output current is rated at 12 mA max
4
Typical Performance Characteristics
T
A
e
25 C
MM54C373 MM74C373
Propagation Delay LATCH
Capacitance
ENABLE to Output vs Load
MM54C373 MM74C373
Data In to Output
Propagation Delay
vs Load Capacitance
MM54C374 MM74C374
CLOCK to Output
Propagation Delay
vs Load Capacitance
TL F 5906 ­ 3
MM54C374 MM74C374
MM54C373 MM74C373
Change in Propagation Delay per
vs Power Supply Voltage
pF of Load Capacitance (Dt
PD
pF)
Output Sink Current vs V
OUT
MM54C374 MM74C374
MM54C373 MM74C373
Source Current vs V
CC
b
V
OUT
MM54C374 MM74C374 Output
MM54C373 MM74C373
TL F 5906 ­ 4
Truth Table
MM54C373 MM74C373
Output
LATCH
D
Q
Disable
ENABLE
L
H
H
H
L
H
L
L
L
L
X
Q
H
X
X
Hi-Z
MM54C374 MM74C374
Output
Clock
D
Q
Disable
L
L
H
H
L
L
L
L
L
L
X
Q
L
H
X
Q
H
X
X
Hi-Z
L
e
Low logic level
H
e
High logic level
X
e
Irrelevant
L
e
Low to high logic level transition
Q
e
Preexisting output level
Hi-Z
e
High impedance output state
5