TL F 5881
MM54C32MM74C32
Quad
2-Input
OR
Gate
February 1988
MM54C32 MM74C32 Quad 2-Input OR Gate
General Description
Employing complementary MOS (CMOS) transistors to
achieve low power and high noise margin these gates pro-
vide the basic functions used in the implementation of digital
integrated circuit systems The N- and P-channel enhance-
ment mode transistors provide a symmetrical circuit with
output swings essentially equal to the supply voltage This
results in high noise immunity over a wide supply voltage
range No DC power other than that caused by leakage cur-
rent is consumed during static conditions All inputs are pro-
tected against static discharge damage
Features
Y
Wide supply voltage range
3 0V to 15V
Y
Guaranteed noise margin
1 0V
Y
High noise immunity
0 45V V
CC
(typ )
Y
Low power
fan out of 2
TTL compatibility
driving 74L
Connection Diagram
Dual-In-Line Package
TL F 5881 1
Top View
Order Number MM54C32 or MM74C32
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
b
0 3V to V
CC
a
0 3V
Operating Temperature Range
MM54C32
b
55 C to
a
125 C
MM74C32
b
40 C to
a
85 C
Storage Temperature Range
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating V
CC
Range
3 0V to 15V
Absolute Maximum V
CC
18V
Lead Temperature
(Soldering 10 seconds)
260 C
DC Electrical Characteristics
Min Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical ``1'' Input Voltage
V
CC
e
5 0V
3 5
V
V
CC
e
10V
8 0
V
V
IN(0)
Logical ``0'' Input Voltage
V
CC
e
5 0V
1 5
V
V
CC
e
10V
2 0
V
V
OUT(1)
Logical ``1'' Output Voltage
V
CC
e
5 0V I
O
e b
10 mA
4 5
V
V
CC
e
10V I
O
e b
10 mA
9 0
V
V
OUT(0)
Logical ``0'' Output Voltage
V
CC
e
5 0V I
O
e
10 mA
0 5
V
V
CC
e
10V I
O
e
10 mA
1 0
V
I
IN(1)
Logical ``1'' Input Current
V
CC
e
15V V
IN
e
15V
0 005
1 0
m
A
I
IN(0)
Logical ``0'' Input Current
V
CC
e
15V V
IN
e
0V
b
1 0
b
0 005
m
A
I
CC
Supply Current
V
CC
e
15V
0 05
15
m
A
CMOS LPTTL INTERFACE
V
IN(1)
Logical ``1'' Input Voltage
54C V
CC
e
4 5V
V
CC
b
1 5
V
74C V
CC
e
4 75V
V
CC
b
1 5
V
V
IN(0)
Logical ``0'' Input Voltage
54C V
CC
e
4 5V
0 8
V
74C V
CC
e
4 75V
0 8
V
V
OUT(1)
Logical ``1'' Output Voltage
54C V
CC
e
4 5V I
O
e b
360 mA
2 4
V
74C V
CC
e
4 75V I
O
e b
360 mA
2 4
V
V
OUT(0)
Logical ``0'' Output Voltage
54C V
CC
e
4 5V I
O
e
360 mA
0 4
V
74C V
CC
e
4 75V I
O
e
360 mA
0 4
V
OUTPUT DRIVE (see 54C 74C Family Characteristics Data Sheet) T
A
e
25 C (short circuit current)
I
SOURCE
Output Source Current
V
CC
e
5 0V V
OUT
e
0V
b
1 75
b
3 3
mA
(P-Channel)
I
SOURCE
Output Source Current
V
CC
e
10V V
OUT
e
0V
b
8 0
b
15
mA
(P-Channel)
I
SINK
Output Sink Current
V
CC
e
5 0V V
OUT
e
V
CC
1 75
3 6
mA
(N-Channel)
I
SINK
Output Sink Current
V
CC
e
10V V
OUT
e
V
CC
8 0
16
mA
(N-Channel)
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
2
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time to
V
CC
e
5 0V
80
150
ns
Logical ``1'' or ``0''
V
CC
e
10V
35
70
ns
C
IN
Input Capacitance
Any Input (Note 2)
5
pF
C
PD
Power Dissipation Capacitance
Per Gate (Note 3)
15
pF
AC Parameters are guaranteed by DC correlated testing
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application
Note
AN-90
Physical Dimensions
inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C32J or MM74C32J
NS Package Number J14A
3
MM54C32MM74C32
Quad
2-Input
OR
Gate
Physical Dimensions
inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM54C32N or MM74C32N
NS Package Number N14A
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SEMICONDUCTOR CORPORATION As used herein
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failure to perform when properly used in accordance
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with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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