Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS V

Power Field Effect Transistor

D2PAK for Surface Mount

NChannel EnhancementMode Silicon Gate

TMOS V is a new technology designed to achieve an onresistance

area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

New Features of TMOS V

Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology

Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETs

Avalanche Energy Specified

IDSS and VDS(on) Specified at Elevated Temperature

Static Parameters are the Same for both TMOS V and TMOS EFET

Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

Vdc

DrainGate Voltage (RGS = 1.0 M

)

VDGR

Vdc

GateSource Voltage -- Continuous

GateSource Voltage

-- NonRepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

52
41

182

Adc

Apk

Total Power Dissipation

Derate above 25

Total Power Dissipation @ TA = 25

C (1)

188

1.25

3.0

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25

)

EAS

406

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

Thermal Resistance

-- Junction to Ambient (1)

0.8

62.5

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Order this document

by MTB52N06V/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MTB52N06V

TMOS POWER FET

52 AMPERES

60 VOLTS

RDS(on) = 0.022 OHM

CASE 418B02, Style 2

D2PAK

Motorola Preferred Device

Motorola, Inc. 1996

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DrainSource Breakdown Voltage

(Cpk

2.0) (3)

(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150

IDSS

--
--

100

Adc

GateBody Leakage Current (VGS =

20 Vdc, VDS = 0)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(Cpk

2.0) (3)

(VDS = VGS, ID = 250

Adc)

Temperature Coefficient (Negative)

VGS(th)

2.0

2.7
6.4

4.0

Vdc

mV/

Static DrainSource OnResistance

(Cpk

2.0) (3)

(VGS = 10 Vdc, ID = 26 Adc)

RDS(on)

0.019

0.022

Ohm

DrainSource OnVoltage

(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150

VDS(on)

--
--

1.4
1.2

Vdc

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

gFS

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

25 Vdc V

0 Vdc

Ciss

1900

2660

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

580

810

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

150

300

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

30 Vd

52 Ad

td(on)

Rise Time

(VDD = 30 Vdc, ID = 52 Adc,

VGS = 10 Vdc

298

600

TurnOff Delay Time

VGS = 10 Vdc,

RG = 9.1

)

td(off)

140

Fall Time

)

110

220

Gate Charge

(See Figure 8)

48 Vd

52 Ad

125

175

(See Figure 8)

(VDS = 48 Vdc, ID = 52 Adc,

( DS

, D

VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 52 Adc, VGS = 0 Vdc)

(IS = 52 Adc, VGS = 0 Vdc, TJ = 150

VSD

--
--

1.0

0.98

1.5

Vdc

Reverse Recovery Time

(See Figure 14)

52 Ad

0 Vd

trr

100

(See Figure 14)

(IS = 52 Adc, VGS = 0 Vdc,

( S

dIS/dt = 100 A/

Reverse Recovery Stored Charge

QRR

0.341

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25

from package to center of die)

--
--

3.5
4.5

--
--

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

Max limit Typ

3 x SIGMA

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

I D

, DRAIN CURRENT

(AMPS)

I D

, DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

and Gate Voltage

TJ, JUNCTION TEMPERATURE (

Figure 5. OnResistance Variation with

Temperature

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

I DSS

, LEAKAGE (nA)

TJ = 25

VGS = 10 V

9 V

8 V

7 V

6 V

5 V

100

7.5

2.5

VDS

10 V

TJ = 55

100

VGS = 10 V

0.035

0.03

100

TJ = 100

TJ = 25

0.023

0.015

VGS = 10 V

15 V

VGS = 10 V
ID = 26 A

1.75

1.5

0.5

0.25

100

125

150

VGS = 0 V

TJ = 125

100

0.02

0.015

0.01

0.021

0.019

0.017

105

100

175

110

3.5

4.5

5.5

6.5

0.025

0.005

110

0.022

0.020

0.018

0.016

1.25

0.75

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are determined

by how fast the FET input capacitance can be charged by
current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE

(pF)

Figure 7. Capacitance Variation

6000

VGS

VDS

VDS = 0 V

5000

4000

3000

2000

VGS = 0 V

TJ = 25

Ciss

Coss

Crss

Ciss

Crss

1000

7000

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

, DRAINT

OSOURCE

VOL

T
AGE

(VOL

TS)

, GA

TET

OSOURCE

VOL

T
AGE

(VOL

TS)

DRAINTOSOURCE DIODE CHARACTERISTICS

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

I S

, SOURCE CURRENT

(AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

100

t, TIME

(ns)

VDD = 30 V
ID = 52 A
VGS = 10 V
TJ = 25

Figure 10. Diode Forward Voltage versus Current

QT, TOTAL CHARGE (nC)

140

ID = 52 A
TJ = 25

1000

100

36
33

3
0

VGS

VDS

td(on)

td(off)

VGS = 0 V
TJ = 25

0.5

0.6

0.7

0.8

0.9

1.1

100

120

0.4

0.3

0.2

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."

Switching between the offstate and the onstate may

traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10

s. In addition the total power

averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of

draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (

E AS

, SINGLE PULSE DRAINT

OSOURCE

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

0.1

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

ALANCHE ENERGY

(mJ)

I D

, DRAIN CURRENT

(AMPS)

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

100

125

VGS = 20 V
SINGLE PULSE
TC = 25

150

Figure 13. Thermal Response

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

0.5

1.5

2.0

2.5

100

125

150

TA, AMBIENT TEMPERATURE (

, POWER DISSIP

TION (W

TTS)

Figure 15. D2PAK Power Derating Curve

JA = 50

C/W

Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size

450 mils x 350 mils

1000

450

250

150

350

100

1 ms

10 ms

ID = 52 A

175

400

200

100

300

t, TIME (s)

r(t)

, NORMALIZED EFFECTIVE

TRANSIENT

THERMAL

RESIST

ANCE

JC(t) = r(t) R

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) R

JC(t)

P(pk)

DUTY CYCLE, D = t1/t2

0.1

0.01

1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.

inches

0.33
8.38

0.08

2.032

0.04

1.016

0.63

17.02

0.42

10.66

0.12
3.05

0.24

6.096

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a

function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R

JA, the thermal resistance

from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:

PD =

TJ(max) TA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25

C, one can

calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.

PD =

175

C 25

C/W

= 3.0 Watts

The 50

C/W for the D2PAK package assumes the use of the

recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 3.0 Watts. There are other
alternatives to achieving higher power dissipation from the

surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R

JA versus drain pad area is shown in Figure 16.

Figure 16. Thermal Resistance versus Drain Pad

Area for the D2PAK Package (Typical)

2.5 Watts

A, AREA (SQUARE INCHES)

Board Material = 0.0625

G10/FR4, 2 oz Copper

TA = 25

3.5 Watts

5 Watts

AMBIENT

(

C/W)

, THERMAL

RESIST

ANCE,

JUNCTION

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC59,
SC70/SOT323, SOD123, SOT23, SOT143, SOT223,
SO8, SO14, SO16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or "tombstoning" may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

ÇÇÇ

ÇÇ

Figure 17. Typical Stencil for DPAK and

D2PAK Packages

SOLDER PASTE
OPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

Always preheat the device.

The delta temperature between the preheat and soldering

should be 100

C or less.*

When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10

The soldering temperature and time shall not exceed

260

C for more than 10 seconds.

When shifting from preheating to soldering, the maximum

temperature gradient shall be 5

C or less.

After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating "profile" for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 189

C. When this type of

furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1
"RAMP"

STEP 2

VENT

"SOAK"

STEP 3

HEATING

ZONES 2 & 5

"RAMP"

STEP 4

HEATING

ZONES 3 & 6

"SOAK"

STEP 5

HEATING

ZONES 4 & 7

"SPIKE"

STEP 6

VENT

STEP 7

COOLING

200

150

100

TIME (3 TO 7 MINUTES TOTAL)

TMAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205

TO 219

PEAK AT

SOLDER JOINT

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

100

150

160

170

140

Figure 18. Typical Solder Heating Profile

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

MTB52N06V

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 418B02

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

STYLE 2:

PIN 1. GATE

2. DRAIN
3. SOURCE
4. DRAIN

SEATING
PLANE

T

0.13 (0.005)

3 PL

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.340

0.380

8.64

9.65

0.380

0.405

9.65

10.29

0.160

0.190

4.06

4.83

0.020

0.035

0.51

0.89

0.045

0.055

1.14

1.40

0.100 BSC

2.54 BSC

0.080

0.110

2.03

2.79

0.018

0.025

0.46

0.64

0.090

0.110

2.29

2.79

0.575

0.625

14.60

15.88

0.045

0.055

1.14

1.40

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals"
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INTERNET: http://DesignNET.com

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

MTB52N06V/D

*MTB52N06V/D*

Part Number MTB52N06V