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MC74HC299

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air

Plastic DIP

SOIC Package

ÎÎÎÎÎÎ

750
500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎÎÎÎ

260

ÎÎÎ

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

Derating -- Plastic DIP: 10 mW/

C from 65

to 125

SOIC Package: 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time

VCC = 2.0 V

(Figure 1)

VCC = 4.5 V
VCC = 6.0 V

ÎÎÎ

0
0
0

ÎÎÎ

1000

500
400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎ

 55 to

ÎÎÎÎ

ÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC 0.1 V

|Iout|

ÎÎÎ

2.0
4.5
6.0

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

1.5

3.15

4.2

ÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC 0.1 V

|Iout|

ÎÎÎ

2.0
4.5
6.0

ÎÎÎÎ

0.3
0.9
1.2

ÎÎÎÎ

0.3
0.9
1.2

ÎÎÎ

0.3
0.9
1.2

ÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

ÎÎÎ

2.0
4.5
6.0

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎ

1.9
4.4
5.9

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

6.0 mA (P/Q)

|Iout|

7.8 mA (P/Q)

ÎÎÎ

4.5
6.0

ÎÎÎÎ

3.98
5.48

ÎÎÎÎ

3.84
5.34

ÎÎÎ

3.70
5.20

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA (Q

)

|Iout|

5.2 mA (Q

)

ÎÎÎ

4.5
6.0

ÎÎÎÎ

3.98
5.48

ÎÎÎÎ

3.84
5.34

ÎÎÎ

3.70
5.20

ÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

ÎÎÎ

2.0
4.5
6.0

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎ

0.1
0.1
0.1

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

6.0 mA (P/Q)

|Iout|

7.8 mA (P/Q)

ÎÎÎ

4.5
6.0

ÎÎÎÎ

0.26
0.26

ÎÎÎÎ

0.33
0.33

ÎÎÎ

0.40
0.40

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA (Q

)

|Iout|

5.2 mA (Q

)

ÎÎÎ

4.5
6.0

ÎÎÎÎ

0.26
0.26

ÎÎÎÎ

0.33
0.33

ÎÎÎ

0.40
0.40

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎ

0.1

ÎÎÎÎ

1.0

ÎÎÎ

1.0

ÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎ

Maximum ThreeState Leakage
Current (QA thru QH)

ÎÎÎÎÎÎÎÎÎÎÎ

Output in HighImpedance State
Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎ

0.5

ÎÎÎÎ

5.0

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply
Current (per Package)

ÎÎÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0

ÎÎÎ

6.0

ÎÎÎÎ

ÎÎÎ

160

ÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND

(Vin or Vout)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.

MC74HC299

HighSpeed CMOS Logic Data
DL129 -- Rev 6

MOTOROLA

AC ELECTRICAL CHARACTERISTICS

(CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

5.0

25
29

ÎÎÎÎ

4.0

20
24

ÎÎÎÎ

3.4

17
20

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to QA

or QH

(Figures 1 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

170

34
29

ÎÎÎÎ

215

43
37

ÎÎÎÎ

255

51
43

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to QA thru QH

(Figures 1 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

160

32
27

ÎÎÎÎ

200

40
34

ÎÎÎÎ

240

48
41

ÎÎÎ

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to QA or QH

(Figures 2 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

175

35
30

ÎÎÎÎ

220

44
37

ÎÎÎÎ

265

53
45

ÎÎÎ

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to QA

thru QH

(Figures 2 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

190

38
32

ÎÎÎÎ

240

48
41

ÎÎÎÎ

285

57
48

ÎÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH

(Figures 3 and 6)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

150

30
26

ÎÎÎÎ

190

38
33

ÎÎÎÎ

225

45
38

ÎÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH

(Figures 3 and 6)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

150

30
26

ÎÎÎÎ

190

38
33

ÎÎÎÎ

225

45
38

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, QA thru QH

(Figures 1 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

60
12
10

ÎÎÎÎ

75
15
13

ÎÎÎÎ

90
18
15

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, QA

or QH

(Figures 1 and 5)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

75
15
13

ÎÎÎÎ

95
19
16

ÎÎÎÎ

110

22
19

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum ThreeState Output Capacitance
(Output in HighImpedance State), QA thru QH

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*, Outputs Enabled

Typical @ 25

C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Package)*, Outputs Enabled

240

* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola HighSpeed CMOS Data Book (DL129/D).

MC74HC299

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

TIMING REQUIREMENTS

(Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Mode Select S1 or S2 to Clock

(Figure 4)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

100

20
17

ÎÎÎÎ

125

25
21

ÎÎÎÎ

150

30
26

ÎÎÎ

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock

(Figure 4)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

100

20
17

ÎÎÎÎ

125

25
21

ÎÎÎÎ

150

30
26

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Mode Select S1 or S2

(Figure 4)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

120

24
20

ÎÎÎÎ

150

30
26

ÎÎÎÎ

180

36
31

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru PH

(Figure 4)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

5
5
5

ÎÎÎÎ

5
5
5

ÎÎÎÎ

5
5
5

ÎÎÎ

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

50
10

ÎÎÎÎ

65
13

ÎÎÎÎ

75
15
13

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

(Figure 1)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

80
16
14

ÎÎÎÎ

100

20
17

ÎÎÎÎ

120

24
20

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Reset

(Figure 2)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

80
16
14

ÎÎÎÎ

100

20
17

ÎÎÎÎ

120

24
20

ÎÎÎ

ÎÎÎÎ

tf, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

1000

500
400

ÎÎÎÎ

1000

500
400

ÎÎÎÎ

1000

500
400

ÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

MC74HC299

HighSpeed CMOS Logic Data
DL129 -- Rev 6

MOTOROLA

FUNCTION TABLE

Inputs

Response

Mode

Reset

Mode

Select

Output

Enables

Clock

Serial

Inputs

PA/QA

PB/QB

PC/QC

PD/QD

PE/QE

PF/QF

PG/QG

PH/QH

Mode

Reset

OE1

OE2

Clock

PA/QA

PB/QB

PC/QC

PD/QD

PE/QE

PF/QF

PG/QG

PH/QH

Reset

QA through QH = Z

Shift
Right

Shift Right: QA through QH = Z; DA

FA; FA

FB; etc.

Right

Shift Right: QA through QH = Z; DA

FA; FA

FB; etc.

Shift Right: DA

FA = QA; FA

FB = QB; etc.

Shift
Left

Shift Left: QA through QH = Z; DH

FH; FH

FG; etc.

Left

Shift Left: QA through QH = Z; DH

FH; FH

FG; etc.

Shift Left: DH

FH = QH; FH

FG = QG; etc.

Parallel
Load

Parallel Load: PN

Hold

Hold: QA through QH = Z; FN = FN

Hold: QN = QN

Z = high impedance
D = data on serial input
F = flipflop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential

operation or clearing of the register is not affected.

PIN DESCRIPTIONS

DATA INPUTS

SA (Pin 11)

Serial data input (Shift Right). Data on this input is shifted

into the shift register on the rising edge of Clock when S2 is
low and S1 is high (shift right mode).

SH (Pin 18)

Serial data input (Shift Left). Data on this input is shifted

into the shift register on the rising edge of Clock when S2 is
high and S1 is low (shift left mode).

PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16)

Parallel data port inputs. Data on these pins can be paral-

lel loaded into the shift register on the rising edge of Clock
when both S1 and S2 are high. For any other combination of
S1 and S2, these pins serve as the outputs of the shift
register.

CONTROL INPUTS

Clock (Pin 12)

Clock input. A lowtohigh transition on this pin shifts the

data at each stage to the next stage (shift right or left mode)
or loads the data at the parallel data inputs into the shift reg-
ister (parallel load mode).

OE1, OE2 (Pins 2, 3)

Activelow output enables. When both OE1 and OE2 are

low, the Outputs QA through QH are enabled. When one or

both output enables are high, the outputs are forced to the
highimpedance state; however, sequential operation or
clearing of the register is not affected.

Reset (Pin 9)

Activelow reset. A low on this pin resets all stages of the

S1, S2 (Pins 1, 19)

Mode select inputs. The levels present at these pins deter-

mine the shift register's mode of operation:

S1 = S2 = Low. Hold.
S1 = Low, S2 High. Shift left.
S1 = High, S2 Low. Shift right.
S1 = S2 = High. Parallel load.

OUTPUTS

, QH

(Pins 8, 17)

Serial data outputs. These are the outputs of the first and

last stages of the shift register, respectively. These outputs
are not 3state outputs and have standard drive capabilities.

QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16)

Parallel data port outputs. Shifted data is present at these

pins when OE1 and OE2 are low. For all other combinations
of OE1 and OE2 these outputs are in the highimpedance
state.

Part Number MC74HC299