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Part Number MC74F382

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Printed on:Mon, Feb 6, 1995 09:49:57
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Document:MC74F382 (5) VIEW
Last saved on:Fri, Feb 3, 1995 16:07:09
4-184
FAST AND LS TTL DATA
4-BIT ARITHMETIC LOGIC UNIT
The MC54/74F382 performs three arithmetic and three logic operations on
two 4-bit words, A and B. Two additional Select input codes force the Function
outputs LOW or HIGH. An Overflow output is provided for convenience in twos
complement arithmetic. A Carry output is provided for ripple expansion. For
high-speed expansion using a Carry Lookahead Generator, refer to the F381
data sheet.
·
Performs Six Arithmetic and Logic Functions
·
Selectable Low (Clear) and High (Preset) Functions
·
LOW Input Loading Minimizes Drive Requirements
·
Carry Output for Ripple Expansion
·
Overflow Output for Twos Complement Arithmetic
CONNECTION DIAGRAM
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
A1
A2
B2
A3
B3
Cn+4
Cn
OVR
B1
A0
B0
S0
S1
S2
F0
9
10
F1 GND
12
11
F3
F2
LOGIC SYMBOL
Cn
S2
S1
S0
Cn+4
OVR
A0
B3
A3
B2
A2
B0 A1 B1
F0
F3
F2
F1
3 4
1
2 19 18 17 16
15
7
6
5
14
13
8
9
11
12
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54, 74
4.5
5.0
5.5
V
TA
Operating Ambient Temperature Range
54
­ 55
25
125
°
C
TA
Operating Ambient Temperature Range
74
0
25
70
°
C
IOH
Output Current -- High
54, 74
­1.0
mA
IOL
Output Current -- Low
54, 74
20
mA
MC54/74F382
4-BIT ARITHMETIC LOGIC UNIT
FAST
TM
SCHOTTKY TTL
ORDERING INFORMATION
MC54FXXXJ
Ceramic
MC74FXXXN
Plastic
MC74FXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
4-185
FAST AND LS TTL DATA
MC54/74F382
LOGIC DIAGRAM
Please note that this diagram is provided
only for the understanding of logic
operations and should not be used to
estimate propagation delays.
Cn
B0
A0
B1
A1
B2
A2
B3
A3
S0
S1
S2
F0
F1
F2
F3
P
G
OVR
Cn+4
F381
ONLY
F382
ONLY
4-186
FAST AND LS TTL DATA
MC54/74F382
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage
VIK
Input Clamp Diode Voltage
­1.2
V
IIN = ­18 mA
VCC = MIN
VOH
Output HIGH Voltage
54, 74
2.5
3.4
V
IOH = ­1.0 mA
VCC = 4.5 V
VOH
Output HIGH Voltage
74
2.7
3.4
V
IOH = ­1.0 mA
VCC = 4.75 V
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 20 mA
VCC = MIN
IIH
Input HIGH Current
20
µ
A
VIN = 2.7 V
VCC = MAX
IIH
Input HIGH Current
100
µ
A
VIN = 7.0 V
VCC = MAX
IIL
Input LOW Current
S0­S2 Inputs
­ 0.6
mA
VIN = 0.5 V
VCC = MAX
IIL
Other Inputs
­ 2.4
mA
VIN = 0.5 V
VCC = MAX
Cn Input
­ 3.0
mA
IOS
Output Short Circuit Current (Note 2)
­ 60
­150
mA
VOUT = 0 V
VCC = MAX
ICC
Power Supply Current
54
81
mA
S0, Cn = HIGH;
Other Inputs GND
VCC = MAX
NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION
Signals applied to the Select inputs S0­S2 determine the
mode of operation, as indicated in the Function Select Table.
An extensive listing of input and output levels is shown in the
Truth Table. The circuit performs the arithmetic functions for
either active HIGH or active LOW operands, with output levels
in the same convention. In the Subtract operating modes, it is
necessary to force a carry (HIGH for active HIGH operands,
LOW for active LOW operands) into the Cn input of the least
significant package. Ripple expansion is illustrated in Figure
1. The overflow output OVR is the Exclusive-OR of Cn + 3 and
Cn+4; a HIGH signal on OVR indicates overflow in twos
complement operation. Typical delays for Figure 1 are given
in Figure 2.
FUNCTION SELECT TABLE
Select
Operation
S0
S1
S2
Operation
L
L
L
Clear
H
L
L
B Minus A
L
H
L
A Minus B
H
H
L
A Plus B
L
L
H
A
B
H
L
H
A + B
L
H
H
AB
H
H
H
Preset
H = HIGH Voltage Level L = LOW Voltage Level
4-187
FAST AND LS TTL DATA
MC54/74F382
Figure 1. 16-Bit Ripple Carry ALU Expansion
SELECT
3
3
Cin
A0­A3 B0­B3
A4­A7 B4­B7
A8­A11 B8­B11
A12­A15 B12­B15
4
4
A
B
Cn
S
F382
Cn+4
OVR
F12­F15
F0­F3
F4­F7
F8­F11
OVERFLOW
Cout
3
4
4
A
B
Cn
S
F382
Cn+4
3
4
4
A
B
Cn
S
F382
Cn+4
3
4
4
A
B
Cn
S
F382
Cn+4
Path Segment
Toward
F
Output
Cn + 4, OVR
Path Segment
Toward
F
Output
Cn + 4, OVR
Ai or Bi to Cn + 4
6.5 ns
6.5 ns
Cn to Cn + 4
6.3 ns
6.3 ns
Cn to Cn + 4
6.3 ns
6.3 ns
Cn to F
8.1
--
Cn to Cn + 4, OVR
--
8.0 ns
Total Delay
27.2 ns
27.1 ns
Figure 2. 16-Bit Delay Tabulation
AC CHARACTERISTICS
Symbol
Parameter
54/74F
54F
74F
Unit
Symbol
Parameter
TA = +25
°
C
TA = ­55 to +125
°
C
TA = 0 to 70
°
C
Unit
Symbol
Parameter
VCC = +5.0 V
VCC = 5.0 V
±
10%
VCC = 5.0 V
±
10%
Unit
Symbol
Parameter
CL = 50 pF
CL = 50 pF
CL = 50 pF
Unit
Symbol
Parameter
Min
Typ
Max
Min
Max
Min
Max
Unit
tPLH
Propagation Delay
3.0
8.1
12
3.0
15
3.0
13
ns
tPHL
Cn to Fi
2.5
5.7
8.0
2.5
11
2.5
9.0
ns
tPLH
Propagation Delay
4.0
10.4
15
4.0
18
4.0
16
ns
tPHL
Any A or B to Any F
3.5
8.2
11
3.5
14
3.5
12
ns
t
PLH
Propagation Delay
6.0
11
15
6.0
21
6.0
16
ns
tPHL
Si to Fi
4.0
8.2
20.5
4.0
23.5
4.0
21.5
ns
tPLH
Propagation Delay
3.5
6.0
8.5
3.5
11.5
3.5
9.5
ns
tPHL
Ai or Bi to Cn + 4
3.0
6.5
9.0
3.0
12.5
3.0
10.5
ns
tPLH
Propagation Delay
7.0
12.5
16.5
7.0
19.5
7.0
17.5
ns
tPHL
Si to OVR or Cn + 4
4.5
9.0
12
4.5
15
4.5
13
ns
tPLH
Propagation Delay
2.5
5.6
8.0
2.5
11
2.5
9.0
ns
tPHL
Cn to Cn + 4
2.5
6.3
9.0
2.5
12
2.5
10
ns
tPLH
Propagation Delay
3.5
8.0
11
3.5
14
3.5
12
ns
tPHL
Cn to OVR
3.5
7.1
10
3.5
13
3.5
11
ns
tPLH
Propagation Delay
6.5
11.5
15.5
6.5
18.5
6.5
16.5
ns
tPHL
Ai or Bi to OVR
5.5
8.0
10.5
5.5
13.5
5.5
11.5
ns