Document Outline

• Revision History
• List of Sections
• Table of Contents
• List of Figures
• List of Tables
• Section 1. General Description
  • 1.1 Contents
  • 1.2 Introduction
  • 1.3 Features
    • 1.3.1 Standard Features of the MC68HC908GT16/MC68HC908GT8
    • 1.3.2 Features of the CPU08
  • 1.4 MCU Block Diagram
  • 1.5 Pin Assignments
  • 1.6 Pin Functions
    • 1.6.1 Power Supply Pins (VDD and VSS)
    • 1.6.2 Oscillator Pins (PTE4/OSC1 and PTE3/OSC2)
    • 1.6.3 External Reset Pin (RST)
    • 1.6.4 External Interrupt Pin (IRQ)
    • 1.6.5 ADC and ICG Power Supply Pins (VDDA and VSSA)
    • 1.6.6 ADC Reference Pins (VREFH and VREFL)
    • 1.6.7 Port A Input/Output (I/O) Pins (PTA7/KBD7…PTA0/KBD0)
    • 1.6.8 Port B I/O Pins (PTB7/AD7…PTB0/AD0)
    • 1.6.9 Port C I/O Pins (PTC6…PTC0)
    • 1.6.10 Port D I/O Pins (PTD7/T2CH1…PTD0/SS)
    • 1.6.11 Port E I/O Pins (PTE4…PTE2, PTE1/RxD, and PTE0/TxD)
• Section 2. Memory Map
  • 2.1 Contents
  • 2.2 Introduction
  • 2.3 Unimplemented Memory Locations
  • 2.4 Reserved Memory Locations
  • 2.5 Input/Output (I/O) Section
• Section 3. Low-Power Modes
  • 3.1 Contents
  • 3.2 Introduction
    • 3.2.1 Wait Mode
    • 3.2.2 Stop Mode
  • 3.3 Analog-to-Digital Converter (ADC)
    • 3.3.1 Wait Mode
    • 3.3.2 Stop Mode
  • 3.4 Break Module (BRK)
    • 3.4.1 Wait Mode
    • 3.4.2 Stop Mode
  • 3.5 Central Processor Unit (CPU)
    • 3.5.1 Wait Mode
    • 3.5.2 Stop Mode
  • 3.6 Internal Clock Generator Module (ICG)
    • 3.6.1 Wait Mode
    • 3.6.2 Stop Mode
  • 3.7 Computer Operating Properly Module (COP)
    • 3.7.1 Wait Mode
    • 3.7.2 Stop Mode
  • 3.8 External Interrupt Module (IRQ)
    • 3.8.1 Wait Mode
    • 3.8.2 Stop Mode
  • 3.9 Keyboard Interrupt Module (KBI)
    • 3.9.1 Wait Mode
    • 3.9.2 Stop Mode
  • 3.10 Low-Voltage Inhibit Module (LVI)
    • 3.10.1 Wait Mode
    • 3.10.2 Stop Mode
  • 3.11 Enhanced Serial Communications Interface Module (SCI)
    • 3.11.1 Wait Mode
    • 3.11.2 Stop Mode
  • 3.12 Serial Peripheral Interface Module (SPI)
    • 3.12.1 Wait Mode
    • 3.12.2 Stop Mode
  • 3.13 Timer Interface Module (TIM1 and TIM2)
    • 3.13.1 Wait Mode
    • 3.13.2 Stop Mode
  • 3.14 Timebase Module (TBM)
    • 3.14.1 Wait Mode
    • 3.14.2 Stop Mode
  • 3.15 Exiting Wait Mode
  • 3.16 Exiting Stop Mode
• Section 4. Resets and Interrupts
  • 4.1 Contents
  • 4.2 Introduction
  • 4.3 Resets
    • 4.3.1 Effects
    • 4.3.2 External Reset
    • 4.3.3 Internal Reset
      • 4.3.3.1 Power-On Reset (POR)
      • 4.3.3.2 Computer Operating Properly (COP) Reset
      • 4.3.3.3 Low-Voltage Inhibit Reset
      • 4.3.3.4 Illegal Opcode Reset
      • 4.3.3.5 Illegal Address Reset
    • 4.3.4 SIM Reset Status Register
  • 4.4 Interrupts
    • 4.4.1 Effects
    • 4.4.2 Sources
      • 4.4.2.1 Software Interrupt (SWI) Instruction
      • 4.4.2.2 Break Interrupt
      • 4.4.2.3 IRQ Pin
      • 4.4.2.4 Internal Clock Generator (ICG)
      • 4.4.2.5 Timer Interface Module 1 (TIM1)
      • 4.4.2.6 Timer Interface Module 2 (TIM2)
      • 4.4.2.7 Serial Peripheral Interface (SPI)
      • 4.4.2.8 Serial Communications Interface (SCI)
      • 4.4.2.9 KBD0…KBD7 Pins
      • 4.4.2.10 Analog-to-Digital Converter (ADC)
      • 4.4.2.11 Timebase Module (TBM)
    • 4.4.3 Interrupt Status Registers
      • 4.4.3.1 Interrupt Status Register 1
      • 4.4.3.2 Interrupt Status Register 2
      • 4.4.3.3 Interrupt Status Register 3
• Section 5. Analog-to-Digital Converter (ADC)
  • 5.1 Contents
  • 5.2 Introduction
  • 5.3 Features
  • 5.4 Functional Description
    • 5.4.1 ADC Port I/O Pins
    • 5.4.2 Voltage Conversion
    • 5.4.3 Conversion Time
    • 5.4.4 Conversion
    • 5.4.5 Accuracy and Precision
  • 5.5 Interrupts
  • 5.6 Low-Power Modes
    • 5.6.1 Wait Mode
    • 5.6.2 Stop Mode
  • 5.7 I/O Signals
    • 5.7.1 ADC Analog Power Pin (VDDA)
    • 5.7.2 ADC Analog Ground Pin (VSSA)
    • 5.7.3 ADC Voltage Reference High Pin (VREFH)
    • 5.7.4 ADC Voltage Reference Low Pin (VREFL)
    • 5.7.5 ADC Voltage In (VADIN)
  • 5.8 I/O Registers
    • 5.8.1 ADC Status and Control Register
    • 5.8.2 ADC Data Register
    • 5.8.3 ADC Clock Register
• Section 6. Break Module (BRK)
  • 6.1 Contents
  • 6.2 Introduction
  • 6.3 Features
  • 6.4 Functional Description
    • 6.4.1 Flag Protection During Break Interrupts
    • 6.4.2 CPU During Break Interrupts
    • 6.4.3 TIM1 and TIM2 During Break Interrupts
    • 6.4.4 COP During Break Interrupts
  • 6.5 Low-Power Modes
    • 6.5.1 Wait Mode
    • 6.5.2 Stop Mode
  • 6.6 Break Module Registers
    • 6.6.1 Break Status and Control Register
    • 6.6.2 Break Address Registers
    • 6.6.3 Break Status Register
    • 6.6.4 Break Flag Control Register
• Section 7. Internal Clock Generator (ICG) Module
  • 7.1 Contents
  • 7.2 Introduction
  • 7.3 Features
  • 7.4 Functional Description
    • 7.4.1 Clock Enable Circuit
    • 7.4.2 Internal Clock Generator
      • 7.4.2.1 Digitally Controlled Oscillator
      • 7.4.2.2 Modulo N Divider
      • 7.4.2.3 Frequency Comparator
      • 7.4.2.4 Digital Loop Filter
    • 7.4.3 External Clock Generator
      • 7.4.3.1 External Oscillator Amplifier
      • 7.4.3.2 External Clock Input Path
    • 7.4.4 Clock Monitor Circuit
      • 7.4.4.1 Clock Monitor Reference Generator
      • 7.4.4.2 Internal Clock Activity Detector
      • 7.4.4.3 External Clock Activity Detector
    • 7.4.5 Clock Selection Circuit
      • 7.4.5.1 Clock Selection Switches
      • 7.4.5.2 Clock Switching Circuit
  • 7.5 Usage Notes
    • 7.5.1 Switching Clock Sources
    • 7.5.2 Enabling the Clock Monitor
    • 7.5.3 Using Clock Monitor Interrupts
    • 7.5.4 Quantization Error in DCO Output
      • 7.5.4.1 Digitally Controlled Oscillator
      • 7.5.4.2 Binary Weighted Divider
      • 7.5.4.3 Variable-Delay Ring Oscillator
      • 7.5.4.4 Ring Oscillator Fine-Adjust Circuit
    • 7.5.5 Switching Internal Clock Frequencies
    • 7.5.6 Nominal Frequency Settling Time
      • 7.5.6.1 Settling to Within 15 Percent
      • 7.5.6.2 Settling to Within 5 Percent
      • 7.5.6.3 Total Settling Time
    • 7.5.7 Trimming Frequency on the Internal Clock Generator
  • 7.6 Low-Power Modes
    • 7.6.1 Wait Mode
    • 7.6.2 Stop Mode
  • 7.7 CONFIG2 Options
    • 7.7.1 External Clock Enable (EXTCLKEN)
    • 7.7.2 External Crystal Enable (EXTXTALEN)
    • 7.7.3 Slow External Clock (EXTSLOW)
    • 7.7.4 Oscillator Enable In Stop (OSCENINSTOP)
  • 7.8 Input/Output (I/O) Registers
    • 7.8.1 ICG Control Register
    • 7.8.2 ICG Multiplier Register
    • 7.8.3 ICG Trim Register
    • 7.8.4 ICG DCO Divider Register
    • 7.8.5 ICG DCO Stage Register
• Section 8. Configuration Register (CONFIG)
  • 8.1 Contents
  • 8.2 Introduction
  • 8.3 Functional Description
• Section 9. Computer Operating Properly (COP) Module
  • 9.1 Contents
  • 9.2 Introduction
  • 9.3 Functional Description
  • 9.4 I/O Signals
    • 9.4.1 COPCLK
    • 9.4.2 STOP Instruction
    • 9.4.3 COPCTL Write
    • 9.4.4 Power-On Reset
    • 9.4.5 Internal Reset
    • 9.4.6 Reset Vector Fetch
    • 9.4.7 COPD (COP Disable)
    • 9.4.8 COPRS (COP Rate Select)
  • 9.5 COP Control Register
  • 9.6 Interrupts
  • 9.7 Monitor Mode
  • 9.8 Low-Power Modes
    • 9.8.1 Wait Mode
    • 9.8.2 Stop Mode
  • 9.9 COP Module During Break Mode
• Section 10. Central Processor Unit (CPU)
  • 10.1 Contents
  • 10.2 Introduction
  • 10.3 Features
  • 10.4 CPU Registers
    • 10.4.1 Accumulator
    • 10.4.2 Index Register
    • 10.4.3 Stack Pointer
    • 10.4.4 Program Counter
    • 10.4.5 Condition Code Register
  • 10.5 Arithmetic/Logic Unit (ALU)
  • 10.6 Low-Power Modes
    • 10.6.1 Wait Mode
    • 10.6.2 Stop Mode
  • 10.7 CPU During Break Interrupts
  • 10.8 Instruction Set Summary
  • 10.9 Opcode Map
• Section 11. FLASH Memory
  • 11.1 Contents
  • 11.2 Introduction
  • 11.3 Functional Description
  • 11.4 FLASH Control Register
  • 11.5 FLASH Page Erase Operation
  • 11.6 FLASH Mass Erase Operation
  • 11.7 FLASH Program/Read Operation
  • 11.8 FLASH Block Protection
    • 11.8.1 FLASH Block Protect Register
    • 11.8.2 ICG User Trim Registers (ICGTR5 and ICGTR3)
  • 11.9 Wait Mode
  • 11.10 Stop Mode
• Section 12. External Interrupt (IRQ)
  • 12.1 Contents
  • 12.2 Introduction
  • 12.3 Features
  • 12.4 Functional Description
  • 12.5 IRQ1 Pin
  • 12.6 IRQ Module During Break Interrupts
  • 12.7 IRQ Status and Control Register
• Section 13. Keyboard Interrupt Module (KBI)
  • 13.1 Contents
  • 13.2 Introduction
  • 13.3 Features
  • 13.4 Functional Description
  • 13.5 Keyboard Initialization
  • 13.6 Low-Power Modes
    • 13.6.1 Wait Mode
    • 13.6.2 Stop Mode
  • 13.7 Keyboard Module During Break Interrupts
  • 13.8 I/O Registers
    • 13.8.1 Keyboard Status and Control Register
    • 13.8.2 Keyboard Interrupt Enable Register
• Section 14. Low-Voltage Inhibit (LVI)
  • 14.1 Contents
  • 14.2 Introduction
  • 14.3 Features
  • 14.4 Functional Description
    • 14.4.1 Polled LVI Operation
    • 14.4.2 Forced Reset Operation
    • 14.4.3 Voltage Hysteresis Protection
    • 14.4.4 LVI Trip Selection
  • 14.5 LVI Status Register
  • 14.6 LVI Interrupts
  • 14.7 Low-Power Modes
    • 14.7.1 Wait Mode
    • 14.7.2 Stop Mode
• Section 15. Monitor ROM (MON)
  • 15.1 Contents
  • 15.2 Introduction
  • 15.3 Features
  • 15.4 Functional Description
    • 15.4.1 Entering Monitor Mode
    • 15.4.2 Data Format
    • 15.4.3 Break Signal
    • 15.4.4 Baud Rate
    • 15.4.5 Commands
  • 15.5 Security
• Section 16. Input/Output (I/O) Ports
  • 16.1 Contents
  • 16.2 Introduction
  • 16.3 Port A
    • 16.3.1 Port A Data Register
    • 16.3.2 Data Direction Register A
    • 16.3.3 Port A Input Pullup Enable Register
  • 16.4 Port B
    • 16.4.1 Port B Data Register
    • 16.4.2 Data Direction Register B
  • 16.5 Port C
    • 16.5.1 Port C Data Register
    • 16.5.2 Data Direction Register C
    • 16.5.3 Port C Input Pullup Enable Register
  • 16.6 Port D
    • 16.6.1 Port D Data Register
    • 16.6.2 Data Direction Register D
    • 16.6.3 Port D Input Pullup Enable Register
  • 16.7 Port E
    • 16.7.1 Port E Data Register
    • 16.7.2 Data Direction Register E
• Section 17. Random-Access Memory (RAM)
  • 17.1 Contents
  • 17.2 Introduction
  • 17.3 Functional Description
• Section 18. Enhanced Serial Communications Interface (ESCI) Module
  • 18.1 Contents
  • 18.2 Introduction
  • 18.3 Features
  • 18.4 Pin Name Conventions
  • 18.5 Functional Description
    • 18.5.1 Data Format
    • 18.5.2 Transmitter
      • 18.5.2.1 Character Length
      • 18.5.2.2 Character Transmission
      • 18.5.2.3 Break Characters
      • 18.5.2.4 Idle Characters
      • 18.5.2.5 Inversion of Transmitted Output
      • 18.5.2.6 Transmitter Interrupts
    • 18.5.3 Receiver
      • 18.5.3.1 Character Length
      • 18.5.3.2 Character Reception
      • 18.5.3.3 Data Sampling
      • 18.5.3.4 Framing Errors
      • 18.5.3.5 Baud Rate Tolerance
      • 18.5.3.6 Receiver Wakeup
      • 18.5.3.7 Receiver Interrupts
      • 18.5.3.8 Error Interrupts
  • 18.6 Low-Power Modes
    • 18.6.1 Wait Mode
    • 18.6.2 Stop Mode
  • 18.7 ESCI During Break Module Interrupts
  • 18.8 I/O Signals
    • 18.8.1 PTE0/TxD (Transmit Data)
    • 18.8.2 PTE1/RxD (Receive Data)
  • 18.9 I/O Registers
    • 18.9.1 ESCI Control Register 1
    • 18.9.2 ESCI Control Register 2
    • 18.9.3 ESCI Control Register 3
    • 18.9.4 ESCI Status Register 1
    • 18.9.5 ESCI Status Register 2
    • 18.9.6 ESCI Data Register
    • 18.9.7 ESCI Baud Rate Register
    • 18.9.8 ESCI Prescaler Register
  • 18.10 ESCI Arbiter
    • 18.10.1 ESCI Arbiter Control Register
    • 18.10.2 ESCI Arbiter Data Register
    • 18.10.3 Bit Time Measurement
    • 18.10.4 Arbitration Mode
• Section 19. System Integration Module (SIM)
  • 19.1 Contents
  • 19.2 Introduction
  • 19.3 SIM Bus Clock Control and Generation
    • 19.3.1 Bus Timing
    • 19.3.2 Clock Startup from POR or LVI Reset
    • 19.3.3 Clocks in Stop Mode and Wait Mode
  • 19.4 Reset and System Initialization
    • 19.4.1 External Pin Reset
    • 19.4.2 Active Resets from Internal Sources
      • 19.4.2.1 Power-On Reset
      • 19.4.2.2 Computer Operating Properly (COP) Reset
      • 19.4.2.3 Illegal Opcode Reset
      • 19.4.2.4 Illegal Address Reset
      • 19.4.2.5 Low-Voltage Inhibit (LVI) Reset
      • 19.4.2.6 Monitor Mode Entry Module Reset (MODRST)
  • 19.5 SIM Counter
    • 19.5.1 SIM Counter During Power-On Reset
    • 19.5.2 SIM Counter During Stop Mode Recovery
    • 19.5.3 SIM Counter and Reset States
  • 19.6 Exception Control
    • 19.6.1 Interrupts
      • 19.6.1.1 Hardware Interrupts
      • 19.6.1.2 SWI Instruction
      • 19.6.1.3 Interrupt Status Registers
    • 19.6.2 Reset
    • 19.6.3 Break Interrupts
    • 19.6.4 Status Flag Protection in Break Mode
  • 19.7 Low-Power Modes
    • 19.7.1 Wait Mode
    • 19.7.2 Stop Mode
  • 19.8 SIM Registers
    • 19.8.1 SIM Break Status Register
    • 19.8.2 SIM Reset Status Register
    • 19.8.3 SIM Break Flag Control Register
• Section 20. Serial Peripheral Interface Module (SPI)
  • 20.1 Contents
  • 20.2 Introduction
  • 20.3 Features
  • 20.4 Pin Name Conventions
  • 20.5 Functional Description
    • 20.5.1 Master Mode
    • 20.5.2 Slave Mode
  • 20.6 Transmission Formats
    • 20.6.1 Clock Phase and Polarity Controls
    • 20.6.2 Transmission Format When CPHA = 0
    • 20.6.3 Transmission Format When CPHA = 1
    • 20.6.4 Transmission Initiation Latency
  • 20.7 Queuing Transmission Data
  • 20.8 Error Conditions
    • 20.8.1 Overflow Error
    • 20.8.2 Mode Fault Error
  • 20.9 Interrupts
  • 20.10 Resetting the SPI
  • 20.11 Low-Power Modes
    • 20.11.1 Wait Mode
    • 20.11.2 Stop Mode
  • 20.12 SPI During Break Interrupts
  • 20.13 I/O Signals
    • 20.13.1 MISO (Master In/Slave Out)
    • 20.13.2 MOSI (Master Out/Slave In)
    • 20.13.3 SPSCK (Serial Clock)
    • 20.13.4 SS (Slave Select)
    • 20.13.5 CGND (Clock Ground)
  • 20.14 I/O Registers
    • 20.14.1 SPI Control Register
    • 20.14.2 SPI Status and Control Register
    • 20.14.3 SPI Data Register
• Section 21. Timebase Module (TBM)
  • 21.1 Contents
  • 21.2 Introduction
  • 21.3 Features
  • 21.4 Functional Description
  • 21.5 Timebase Register Description
  • 21.6 Interrupts
  • 21.7 Low-Power Modes
    • 21.7.1 Wait Mode
    • 21.7.2 Stop Mode
• Section 22. Timer Interface Module (TIM)
  • 22.1 Contents
  • 22.2 Introduction
  • 22.3 Features
  • 22.4 Pin Name Conventions
  • 22.5 Functional Description
    • 22.5.1 TIM Counter Prescaler
    • 22.5.2 Input Capture
    • 22.5.3 Output Compare
      • 22.5.3.1 Unbuffered Output Compare
      • 22.5.3.2 Buffered Output Compare
    • 22.5.4 Pulse Width Modulation (PWM)
      • 22.5.4.1 Unbuffered PWM Signal Generation
      • 22.5.4.2 Buffered PWM Signal Generation
      • 22.5.4.3 PWM Initialization
  • 22.6 Interrupts
  • 22.7 Low-Power Modes
    • 22.7.1 Wait Mode
    • 22.7.2 Stop Mode
  • 22.8 TIM During Break Interrupts
  • 22.9 I/O Signals
  • 22.10 I/O Registers
    • 22.10.1 TIM Status and Control Register
    • 22.10.2 TIM Counter Registers
    • 22.10.3 TIM Counter Modulo Registers
    • 22.10.4 TIM Channel Status and Control Registers
    • 22.10.5 TIM Channel Registers
• Section 23. Electrical Specifications
  • 23.1 Contents
  • 23.2 Introduction
  • 23.3 Absolute Maximum Ratings
  • 23.4 Functional Operating Range
  • 23.5 Thermal Characteristics
  • 23.6 5.0-V DC Electrical Characteristics
  • 23.7 3.0-V DC Electrical Characteristics
  • 23.8 5.0-V Control Timing
  • 23.9 3.0-V Control Timing
  • 23.10 Internal Oscillator Characteristics
  • 23.11 External Oscillator Characteristics
  • 23.12 Trimmed Accuracy of the Internal Clock Generator
    • 23.12.1 2.7-Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics
    • 23.12.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics
  • 23.13 Output High-Voltage Characteristics
  • 23.14 Output Low-Voltage Characteristics
  • 23.15 Typical Supply Currents
  • 23.16 ADC Characteristics
  • 23.17 5.0-V SPI Characteristics
  • 23.18 3.0-V SPI Characteristics
  • 23.19 Timer Interface Module Characteristics
  • 23.20 Memory Characteristics
• Section 24. Mechanical Specifications
  • 24.1 Contents
  • 24.2 Introduction
  • 24.3 42-Pin Shrink Dual in-Line Package (SDIP)
  • 24.4 44-Pin Plastic Quad Flat Pack (QFP)
• Section 25. Ordering Information
  • 25.1 Contents
  • 25.2 Introduction
  • 25.3 MC Order Numbers