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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 0

Motorola, Inc. 1995

10/95

Product Preview

8-Bit Serial or Parallel-Input/

Serial-Output Shift Register

HighPerformance SiliconGate CMOS

The MC54/74HC165A is identical in pinout to the LS165. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This device is an 8bit shift register with complementary outputs from the

last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).

The 2input NOR clock may be used either by combining two independent

clock sources or by designating one of the clock inputs to act as a clock
inhibit.

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard
No. 7A

Chip Complexity: 286 FETs or 71.5 Equivalent Gates

FUNCTION TABLE

Inputs

Internal Stages

Output

Operation

Serial Shift/

Parallel Load

Clock

Inhibit

A H

Operation

...

Asynchronous Parallel Load

H
H

L
L

X
X

QAn
QAn

QGn
QGn

Serial Shift via Clock

H
H

L
L

X
X

QAn
QAn

QGn
QGn

Serial Shift via Clock Inhibit

H
H

X
H

H
X

X
X

No Change

Inhibited Clock

No Change

No Clock

X = don't care

QAn QGn = Data shifted from the preceding stage

This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.

MC54/74HC165A

PIN ASSIGNMENT

CLOCK INHIBIT

VCC

CLOCK

SERIAL SHIFT/

PARALLEL LOAD

GND

D SUFFIX

SOIC PACKAGE

CASE 751B05

N SUFFIX

PLASTIC PACKAGE

CASE 64808

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

J SUFFIX

CERAMIC PACKAGE

CASE 62010

DT SUFFIX

TSSOP PACKAGE

CASE 948F01

LOGIC DIAGRAM

PIN 16 = VCC
PIN 8 = GND

PARALLEL

DATA

INPUTS

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

CLOCK

CLOCK INHIBIT

SERIAL

DATA

OUTPUTS

MC54/74HC165A

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic or Ceramic DIP

SOIC Package

TSSOP Package

ÎÎÎÎÎÎ

750
500
450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

260
300

ÎÎÎ

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

Derating -- Plastic DIP: 10 mW/

C from 65

to 125

Ceramic DIP: 10 mW/

C from 100

to 125

SOIC Package: 7 mW/

C from 65

to 125

TSSOP Package: 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time

VCC = 2.0 V

(Figure 1)

VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V

ÎÎÎ

0
0
0

ÎÎÎ

1000

600
500
400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC 0.1 V
|Iout|

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC 0.1 V
|Iout|

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

0.5
0.9

1.35
1.80

ÎÎÎÎ

0.5
0.9

1.35
1.80

ÎÎÎÎ

0.5
0.9

1.35
1.80

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL
|Iout|

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

1.9
4.4
5.9

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0
4.5
6.0

ÎÎÎ

2.48
3.98
5.48

ÎÎÎÎ

2.34
3.84
5.34

ÎÎÎÎ

2.20
3.70
5.20

ÎÎÎ

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND

(Vin or Vout)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC165A

HighSpeed CMOS Logic Data
DL129 -- Rev 6

MOTOROLA

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL
|Iout|

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

0.1
0.1
0.1

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0
4.5
6.0

ÎÎÎ

0.26
0.26
0.26

ÎÎÎÎ

0.33
0.33
0.33

ÎÎÎÎ

0.40
0.40
0.40

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

0.1

ÎÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply
Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND
Iout = 0

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS

(CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

10
15
30
50

ÎÎÎÎ

14
28
45

ÎÎÎÎ

12
25
40

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH

(Figures 1 and 8)

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

110

36
22
19

ÎÎÎÎ

125

45
26
23

ÎÎÎÎ

160

60
32
28

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH

(Figures 2 and 8)

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

85
57
25
19

ÎÎÎÎ

96
63
29
23

ÎÎÎÎ

106

71
32
27

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input H to QH or QH

(Figures 3 and 8)

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

110

36
22
19

ÎÎÎÎ

125

45
26
23

ÎÎÎÎ

160

60
32
28

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

75
27
15
13

ÎÎÎÎ

95
32
19
16

ÎÎÎÎ

110

36
22
19

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25

C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Package)*

* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola HighSpeed CMOS Data Book (DL129/D).

MC54/74HC165A

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

TIMING REQUIREMENTS

(Input tr = tf = 6 ns)

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

ÎÎÎÎ

 55 to

ÎÎÎÎ

ÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load

(Figure 4)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

75
30
15
13

ÎÎÎÎ

95
40
19
16

ÎÎÎ

110

55
22
19

ÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)

(Figure 5)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

75
30
15
13

ÎÎÎÎ

95
40
19
16

ÎÎÎ

110

55
22
19

ÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)

(Figure 6)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

75
30
15
13

ÎÎÎÎ

95
40
19
16

ÎÎÎ

110

55
22
19

ÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Clock to Clock Inhibit

(Figure 7)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

75
30
15
13

ÎÎÎÎ

95
40
19
16

ÎÎÎ

110

55
22
19

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs

(Figure 4)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

1
1
1
1

ÎÎÎÎ

1
1
1
1

ÎÎÎ

1
1
1
1

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA

(Figure 5)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

1
1
1
1

ÎÎÎÎ

1
1
1
1

ÎÎÎ

1
1
1
1

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load

(Figure 6)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

1
1
1
1

ÎÎÎÎ

1
1
1
1

ÎÎÎ

1
1
1
1

ÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Clock to Clock Inhibit

(Figure 7)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

75
30
15
13

ÎÎÎÎ

95
40
19
16

ÎÎÎ

110

55
22
19

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock (or Clock Inhibit)

(Figure 1)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

70
27
15
13

ÎÎÎÎ

90
32
19
16

ÎÎÎ

100

36
22
19

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse width, Serial Shift/Parallel Load

(Figure 2)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

70
27
15
13

ÎÎÎÎ

90
32
19
16

ÎÎÎ

100

36
22
19

ÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎÎ

1000

800
500
400

ÎÎÎÎ

1000

800
500
400

ÎÎÎ

1000

800
500
400

ÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

Part Number MC54/74HC165A