ChipFind - Datasheet

Part Number MC33493

Download:  PDF   ZIP
This document contains information on a new product under development. Motorola
reserves the right to change or discontinue this product without notice.
© Motorola, Inc., 2002
DATA
GND
XTAL0
REXT
CFSK
VCC
RFOUT
GNDRF
VCC
ENABLE
1
2
3
7
4
5
6
8
13
12
11
10
9
14
XTAL1
DATACLK
MODE
BAND
PIN CONNECTIONS
FEATURES
·
Selectable frequency bands:
315-434MHz and 868-928MHz
·
OOK and FSK modulation
·
Adjustable output power range
·
Fully integrated VCO
·
Supply voltage range: 1.9-3.6V
·
Very low standby current: 0.1nA @ T
A
=25
°
C
·
Low supply voltage shutdown
·
Data clock output for microcontroller
·
Extended temperature range: -40
°
C to 125
°
C
·
Low external component count
·
Typical application compliant with ETSI standard
Ordering Information
Device
Ambiant
Temperature
Range
Package
MC33493
DTB
-40
°
C to
125
°
C
TSSOP14
Technical Data
TANGO3
MC33493/D
Rev. 1.6, 6/2002
PLL tuned UHF
Transmitter for Data
Transfer Applications
Figure 1: Simplified block diagram
F
r
e
e
s
c
a
l
e

S
e
m
i
c
o
n
d
u
c
t
o
r
,

I














































Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
2
MC33493 Technical Data
MOTOROLA
PIN FUNCTION DESCRIPTION
PIN FUNCTION DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Notes:
1 Human Body model, AEC-Q100-002 Rev. C.
2 Machine Model, AEC-Q100-003 Rev. E.
TRANSMITTER FUNCTIONAL DESCRIPTION
MC33493 is a PLL tuned low power UHF transmitter. The different modes of operation are controlled by the
microcontroller through several digital input pins. The power supply voltage ranges from 1.9V to 3.6V allowing
operation with a single lithium cell.
PHASE LOCKED LOOP AND LOCAL OSCILLATOR
The VCO is a completely integrated relaxation oscillator. The Phase Frequency Detector (PFD) and the loop filter
are fully integrated. The exact output frequency is equal to: f
RFOUT
= f
XTAL
x [PLL Divider Ratio]. The frequency
band of operation is selected through the BAND pin.
Table 1 provides details for each frequency band selection.
Pin
Name
Description
1
DATACLK
Clock output to the microcontroller
2
DATA
Data input
3
BAND
Frequency band selection
4
GND
Ground
5
XTAL1
Reference oscillator input
6
XTAL0
Reference oscillator output
7
REXT
Power amplifier output current setting input
8
CFSK
FSK switch output
9
VCC
Power supply
10
RFOUT
Power amplifier output
11
GNDRF
Power amplifier ground
12
VCC
Power supply
13
ENABLE
Enable input
14
MODE
Modulation type selection input
Parameter
Symbol
Value
Unit
Supply Voltage
V
CC
V
GND
- 0.3 to 3.7
V
Voltage Allowed on Each Pin
V
GND
- 0.3
to V
CC
+ 0.3
V
ESD HBM Voltage Capability on Each Pin (note 1)
±
2000
V
ESD MM Voltage Capability on Each Pin (note 2)
±
150
V
Storage Temperature
Ts
-65 to +150
°
C
Junction Temperature
Tj
+150
°
C
F
r
e
e
s
c
a
l
e

S
e
m
i
c
o
n
d
u
c
t
o
r
,

I














































Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
RF OUTPUT STAGE
MOTOROLA
MC33493 Technical Data
3
Table 1: Band selection and associated divider ratios
An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the
RF output stage is disabled.
RF OUTPUT STAGE
The output stage is a single ended square wave switched current source. Harmonics are present in the output
current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical
application demonstrates compliance to ETSI standard.
A resistor R
ext
connected to the REXT pin controls the output power allowing a trade-off between radiated power
and current consumption.
The output voltage is internally clamped to V
cc
±
2V
be
(typ. V
cc
±
1.5V @ T
A
=25
°
C).
MODULATION
A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation
is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output
stage state:
DATA=0
output stage off,
DATA=1
output stage on.
If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This
modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the
external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel.
The logic level applied on pin DATA controls the state of this internal switch:
DATA=0
switch off,
DATA=1
switch on.
DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty
cycle cannot exceed
±
1 reference period (
±
75ns for a 13.56MHz crystal).
This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation
multiplied by the PLL Divider Ratio (see table 1).
BAND Input
Level
Frequency
Band (MHz)
PLL Divider
Ratio
Crystal Oscillator
Frequency (MHz)
High
315
32
9.84
434
13.56
Low
868
64
F
r
e
e
s
c
a
l
e

S
e
m
i
c
o
n
d
u
c
t
o
r
,

I














































Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
4
MC33493 Technical Data
MOTOROLA
MICROCONTROLLER INTERFACE
Figure 2: Crystal pulling configurations
MICROCONTROLLER INTERFACE
Four digital input pins (ENABLE, DATA, BAND and MODE) enable the circuit to be controlled by a
microcontroller. It is recommended to configure the band frequency and the modulation type before enabling the
circuit.
One digital output (DATACLK) provides to the microcontroller a reference frequency for data clocking. This
frequency is equal to the crystal oscillator frequency divided by 64 (see table 2).
Table 2: DATACLK frequency vs crystal oscillator frequency
STATE MACHINE
Figure 3 details the state machine.
Crystal Oscillator Frequency (MHz)
DATACLK Frequency (kHz)
9.84
154
13.56
212
F
r
e
e
s
c
a
l
e

S
e
m
i
c
o
n
d
u
c
t
o
r
,

I














































Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
STATE MACHINE
MOTOROLA
MC33493 Technical Data
5
Figure 3: State machine
State 1:
The circuit is in standby mode and draws only a leakage current from the power supply.
State 2:
In this state, the PLL is out of the lock-in range. Therefore the RF output stage is switched off preventing RF
transmission. Data clock is available on pin DATACLK. Each time the device is enabled, the state machine
passes through this state.
State 3:
In this state, the PLL is within the lock-in range. If t<t
PLL_lock_in
then the PLL can still be in acquisition mode. If
t
t
PLL_lock_in
, then the PLL is locked.
Data entered on pin DATA are output on pin RFOUT according to the modulation selected by the level applied on
pin MODE.
State 4:
When the supply voltage falls below the shutdown voltage threshold (V
SDWN
) the whole circuit is switched off.
Applying a low level on pin ENABLE is the only condition to get out of this state.
Figure 4 shows the waveforms of the main signals for a typical application cycle.
State 2
PLL out of lock-in range
No RF output
State 1
Standby mode
ENABLE=1
PLL in
lock-in range
V
battery
< V
shutdown
ENABLE=0
Power ON
AND ENABLE=0
State 3
Transmission mode
ENABLE=0
State 4
Shutdown mode
PLL out of
lock-in range
F
r
e
e
s
c
a
l
e

S
e
m
i
c
o
n
d
u
c
t
o
r
,

I














































Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.