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MOTOROLA CMOS LOGIC DATA

MC14580B

4 x 4 Multiport Register

The MC14580B is a 4 by 4 multiport register useful in small scratch pad

memories, arithmetic operations when coupled with an adder, and other data
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.

Address changing and data entry occur on the rising edge of the clock.

When the write enable input is low, the contents of any word may be
accessed but not altered.

No Restrictions on Clock Input Rise or Fall Times

3State Outputs

Single Phase Clocking

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Capable of Driving Two Lowpower TTL Loads or one Lowpower
Schottky TTL Load Over the Rated Temperature Range

Pin Compatible with CD40108

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

0.5 to + 18.0

Vin, Vout Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

Iin, Iout

Input or Output Current (DC or Transient),
per Pin

Power Dissipation, per Package

500

Tstg

Storage Temperature

65 to + 150

Lead Temperature (8Second Soldering)

260

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:

Plastic "P and D/DW" Packages: 7.0 mW/

C From 65

C To 125

Ceramic "L" Packages: 12 mW/

C From 100

C To 125

BLOCK DIAGRAM

CLOCK

20
19

19
18

DATA

INPUT

R1B

R0B

R1A

R0A

DECODER

3STATE A

4
5
6
7

22
23

2
1

3STATE B

4 X 4

MEMORY

VDD = PIN 24

VSS = PIN 12

D0
D1
D2
D3

Q0A
Q1A

Q2A

Q3A

Q0B
Q1B

Q2B

Q3B

WORD A
OUTPUT

WORD B
OUTPUT

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 3
1/94

MC14580B

L SUFFIX

CERAMIC
CASE 623

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBDW

SOIC

TA = 55

to 125

C for all packages.

P SUFFIX

PLASTIC

CASE 709

DW SUFFIX

SOIC

CASE 751E

PIN ASSIGNMENT

Q2A

Q0A

3STATE A

Q2B

Q3B

WRITE 0

Q3A

Q1A

3STATE B

Q0B

Q1B

VDD

CLOCK

READ 0A

READ 1A

READ 0B

VSS

READ 1B

WRITE 1

MOTOROLA CMOS LOGIC DATA

MC14580B
2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

 55

125

Unit

Characteristic

Symbol

VDD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

"0" Level

Vin = VDD or 0

VOL

5.0

10
15

--
--
--

0.05
0.05
0.05

--
--
--

0
0
0

0.05
0.05
0.05

--
--
--

0.05
0.05
0.05

Vdc

"1" Level

Vin = 0 or VDD

VOH

5.0

10
15

4.95
9.95

14.95

--
--
--

4.95
9.95

14.95

5.0

10
15

--
--
--

4.95
9.95

14.95

--
--
--

Vdc

Input Voltage

"0" Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10
15

--
--
--

1.5
3.0
4.0

--
--
--

2.25
4.50
6.75

1.5
3.0
4.0

--
--
--

1.5
3.0
4.0

Vdc

"1" Level

(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10
15

3.5
7.0

--
--
--

3.5
7.0

2.75
5.50
8.25

--
--
--

3.5
7.0

--
--
--

Vdc

Output Drive Current

(VOH = 2.5 Vdc)

Source

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

IOH

5.0
5.0

10
15

3.0

0.64

1.6
4.2

--
--
--
--

2.4

0.51

1.3
3.4

4.2

0.88

2.25

8.8

--
--
--
--

1.7

0.36

0.9
2.4

--
--
--
--

mAdc

(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

IOL

5.0

10
15

0.64

1.6
4.2

--
--
--

0.51

1.3
3.4

0.88
2.25

8.8

--
--
--

0.36

0.9
2.4

--
--
--

mAdc

Input Current

Iin

0.1

0.00001

0.1

1.0

Adc

Input Capacitance

(Vin = 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

IDD

5.0

10
15

--
--
--

5.0

10
20

--
--
--

0.010
0.020
0.030

5.0

10
20

--
--
--

150
300
600

Adc

Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

5.0

10
15

IT = (1.18

A/kHz) f + IDD

IT = (1.91

A/kHz) f + IDD

IT = (2.67

A/kHz) f + IDD

Adc

ThreeState Leakage Current

ITL

0.1

0.0001

0.1

3.0

Adc

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

** The formulas given are for the typical characteristics only at 25

To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in

A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must

be left open.

MOTOROLA CMOS LOGIC DATA

MC14580B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS*

(CL = 50 pF, TA = 25

Characteristic

Symbol

VDD

Min

Typ #

Max

Unit

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH, tTHL

(Figures 3 and 6)

5.0

10
15

--
--
--

100

50
40

200
100

Propagation Delay Time

Clock to Output

tPLH, tPHL

(Figures 3 and 6)

5.0

10
15

--
--
--

650
250
170

1300

500
340

Write Enable Setup Time

(Enabling a Write or Read)

tsu

(Figure 5)

5.0

10
15

800
300
200

400
150
100

--
--
--

Write Enable Removal Time

(Disabling a Write or Read)

trem

(Figure 5)

5.0

10
15

0
0
0

100

50
35

--
--
--

Setup Time**

Address, Data to Clock

tsu

(Figure 3)

5.0

10
15

50
30
25

0
0

--
--
--

Hold Time**

Clock to Address, Data

(Figure 3)

5.0

10
15

480
195
150

160

65
50

--
--
--

3State Enable/Disable Delay Time

tPHZ, tPLZ
tPZH, tPZL

(Figures 4 and 7)

5.0

10
15

--
--
--

130

60
45

260
120

Clock Pulse Width

(Figure 3)

5.0

10
15

820
330
220

410
165

110

--
--
--

** When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected

and data is valid after the propagation delays listed in the Switching Characteristics Table.

Figure 1. Output Drive Current Test Circuit

Sink Current

Source Current

Position of S1

VGS =

VDD

VDS =

Vout

Vout VDD

EXTERNAL

POWER

SUPPLY

Vout

IDS

VDD

VSS

PULSE

GENERATOR

VDD

VSS

WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3

Q0A

Q1A

Q2A

Q3A

Q0B

Q1B

Q2B

Q3B

MOTOROLA CMOS LOGIC DATA

MC14580B
4

Figure 2. Power Dissipation Test Circuit and Waveforms (3State Inputs are High)

PULSE

GENERATOR

PULSE

GENERATOR

PULSE

GENERATOR

VDD

IDD

W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3

Q0A

Q1A

Q2A

Q3A

Q0B

Q1B

Q2B

Q3B

VSS

REPETITIVE WAVEFORMS

P.G. 1

P.G. 2

P.G. 3

OUTPUT

Qn A, B

Figure 3.

Figure 4.

CLOCK

ADDRESS DATA

tw(H)

tw(L)

VDD

VSS

VDD

VSS

VOH

VOL

50%

tsu

50%

tPLH, tPHL

tTLH, tTHL

50%

90%

10%

3STATE

A OR B

VDD

VSS

VOH

VOL

VOH

VOL

tPHZ

90%

50%

10%

90%

10%

tPZL

tPZH

tPZL

CLOCK

tsu

trem

50%

VDD

VSS

VDD

VSS

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

1 k

CONNECT TO VCC WHEN TESTING tPLZ AND tPZL

CONNECT TO GND WHEN TESTING tPHZ AND tPZH

Figure 5.

Figure 6. Test Circuit

Figure 7. Test Circuit

MOTOROLA CMOS LOGIC DATA

MC14580B

LOGIC DIAGRAM

CLOCK

R0A

R0B

3STATE A

R1A

R1B

C
D
3STATE

3STATE B

Q3A

Q2A

Q1A

Q0A

Q3B

Q2B

Q1B

Q0B

TRUTH TABLE

Clock

Write 1

Write 0

Read 1A

Read 0A

Read 1B

Read 0B 3State A

3State B

QnA

QnB

Change

Dn to

word 0

Contents

of word 1
displayed

Contents

of word 2
displayed

Word 0

not

altered

Contents

of word 1
displayed

Contents

of word 2
displayed

Z = High Impedance
X = Don't Care

Part Number MC14580B