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MOTOROLA CMOS LOGIC DATA

MC14553B

3-Digit BCD Counter

The MC14553B 3digit BCD counter consists of 3 negative edge triggered

BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.

An onchip oscillator provides the lowfrequency scanning clock which

drives the multiplexer output selector.

This device is used in instrumentation counters, clock displays, digital

panel meters, and as a building block for general logic applications.

TTL Compatible Outputs

OnChip Oscillator

Cascadable

Clock Disable Input

Pulse Shaping Permits Very Slow Rise Times on Input Clock

Output Latches

Master Reset

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

0.5 to + 18.0

Vin, Vout Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

Iin

Input Current (DC or Transient), per Pin

Iout

Output Current (DC or Transient), per Pin

+ 20

Power Dissipation, per Package

500

Tstg

Storage Temperature

65 to + 150

Lead Temperature (8Second Soldering)

260

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:

Plastic "P and D/DW" Packages: 7.0 mW/

C From 65

C To 125

Ceramic "L" Packages: 12 mW/

C From 100

C To 125

TRUTH TABLE

Inputs

Outputs

Master

Reset

Clock

Disable

Outputs

No Change

Advance

No Change

Advance

No Change

Latched

Q0 = Q1 = Q2 = Q3 = 0

X = Don't Care

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 3
1/94

MC14553B

BLOCK DIAGRAM

This device contains protection circuitry to

guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

L SUFFIX

CERAMIC
CASE 620

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBDW

SOIC

TA = 55

to 125

C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

VDD = PIN 16

VSS = PIN 8

CLOCK

DIS

O.F.

DS1

DS2

DS3

CIA

CIB

MOTOROLA CMOS LOGIC DATA

MC14553B
2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

 55

125

Unit

Characteristic

Symbol

VDD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

"0" Level

Vin = VDD or 0

VOL

5.0

10
15

--
--
--

0.05
0.05
0.05

--
--
--

0
0
0

0.05
0.05
0.05

--
--
--

0.05
0.05
0.05

Vdc

"1" Level

Vin = 0 or VDD

VOH

5.0

10
15

4.95
9.95

14.95

--
--
--

4.95
9.95

14.95

5.0

10
15

--
--
--

4.95
9.95

14.95

--
--
--

Vdc

Input Voltage

"0" Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10
15

--
--
--

1.5
3.0
4.0

--
--
--

2.25
4.50
6.75

1.5
3.0
4.0

--
--
--

1.5
3.0
4.0

Vdc

"1" Level

(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10
15

3.5
7.0

--
--
--

3.5
7.0

2.75
5.50
8.25

--
--
--

3.5
7.0

--
--
--

Vdc

Output Drive Current

(VOH = 4.6 Vdc)

Source --

(VOH = 9.5 Vdc)

Pin 3

(VOH = 13.5 Vdc)

IOH

5.0

10
15

0.25
0.62

1.8

--
--
--

0.2
0.5
1.5

0.36

0.9
3.5

--
--
--

0.14
0.35

1.1

--
--
--

mAdc

(VOH = 4.6 Vdc)

Source --

(VOH = 9.5 Vdc)

Other

(VOH = 13.5 Vdc)

Outputs

5.0

10
15

0.64

1.6
4.2

--
--
--

0.51

1.3
3.4

0.88
2.25

8.8

--
--
--

0.36

0.9
2.4

--
--
--

mAdc

(VOL = 0.4 Vdc)

Sink --

(VOL = 0.5 Vdc)

Pin 3

(VOL = 1.5 Vdc)

IOL

5.0

10
15

0.5
1.1
1.8

--
--
--

0.4
0.9
1.5

0.88
2.25

8.8

--
--
--

0.28
0.65
1.20

--
--
--

mAdc

(VOL = 0.4 Vdc) Sink -- Other
(VOL = 0.5 Vdc)

Outputs

(VOL = 1.5 Vdc)

5.0

10
15

3.0
6.0

--
--
--

2.5
5.0

4.0
8.0

--
--
--

1.6
3.5

--
--
--

mAdc

Input Current

Iin

0.1

0.00001

0.1

1.0

Adc

Input Capacitance

(Vin = 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

MR = VDD

IDD

5.0

10
15

--
--
--

5.0

10
20

--
--
--

0.010
0.020
0.030

5.0

10
20

--
--
--

150
300
600

Adc

Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

5.0

10
15

IT = (0.35

A/kHz) f + IDD

IT = (0.85

A/kHz) f + IDD

IT = (1.50

A/kHz) f + IDD

Adc

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

** The formulas given are for the typical characteristics only at 25

To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in

A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATA

MC14553B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS

(CL = 50 pF, TA = 25

Characteristic

Figure

Symbol

VDD

Min

Typ #

Max

Unit

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,

tTHL

5.0

10
15

--
--
--

100

50
40

200
100

Clock to BCD Out

tPLH,

tPHL

5.0

10
15

--
--
--

900
500
200

1800
1000

400

Clock to Overflow

tPHL

5.0

10
15

--
--
--

600
400
200

1200

800
400

Reset to BCD Out

tPHL

5.0

10
15

--
--
--

900
500
300

1800
1000

600

Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time

tsu

5.0

10
15

600
400
200

300
200
100

--
--
--

Removal Time

Latch Enable to Clock

trem

5.0

10
15

80
10

200

70
50

--
--
--

Clock Pulse Width

tWH(cl)

5.0

10
15

550
200
150

275
100

--
--
--

Reset Pulse Width

tWH(R)

5.0

10
15

1200

600
450

600
300
225

--
--
--

Reset Removal Time

trem

5.0

10
15

180

50
30

--
--
--

Input Clock Frequency

fcl

5.0

10
15

--
--
--

1.5
5.0
7.0

0.9
2.5
3.5

MHz

Input Clock Rise Time

tTLH

5.0

10
15

Limit

Disable, MR, Latch Enable

Rise and Fall Times

tTLH,

tTHL

5.0

10
15

--
--
--

5.0
4.0

Scan Oscillator Frequency

(C1 measured in

fosc

5.0

10
15

--
--
--

1.5/C1
4.2/C1
7.0/C1

--
--
--

* The formulas given are for the typical characteristics only at 25

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

MOTOROLA CMOS LOGIC DATA

MC14553B
4

Figure 1. 3Digit Counter Timing Diagram (Reference Figure 3)

1000

999

998

997

996

995

994

993

992

991

990

901

900

899

101

100

1
1

UNITS CLOCK

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

TENS CLOCK

TENS Q0

TENS Q3

HUNDREDS

CLOCK

HUNDREDS Q0

HUNDREDS Q3

DISABLE

OVERFLOW

MASTER

RESET

SCAN

OSCILLATOR

DIGIT SELECT 1

DIGIT SELECT 2

DIGIT SELECT 3

UP AT 80

UP AT 980

UP AT 800

(DISABLES CLOCK WHEN HIGH)

UNITS

TENS

HUNDREDS

PULSE

GENERATOR

(a)

VDD

Q3
Q2
Q1
Q0

O.F.

DS1
DS2
DS3

VSS

DIS

GENERATOR

(b)

VDD

Q3
Q2
Q1
Q0

O.F.

DS1
DS2
DS3

VSS

DIS

GENERATOR

20 ns

90%

10%

tPLH

tPHL

50%

tTHL

tTLH

10%

90%

50%

1/fcl

tWL(cl)

999

1000

tTLH

50%

OVERFLOW

BCD OUT

CLOCK

90%

10%

trem

tPHL, tPLH

50%

tWH(R)

tsu

tPHL

MASTER RESET

BCD OUT

LATCH
ENABLE

CLOCK

Figure 2. Switching Time Test Circuits and Waveforms

tsu

tPHL

MOTOROLA CMOS LOGIC DATA

MC14553B

OPERATING CHARACTERISTICS

The MC14553B threedigit counter, shown in Figure 3,

consists of three negative edgetriggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits stor-
age of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time divi-
sion multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.

An onchip oscillator provides the low frequency scanning

clock which drives the multiplexer output selector. The fre-
quency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one

pulse for every 1000 counts.

The Master Reset input, when taken high, initializes the

three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue op-
erating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been re-
set if Latch Enable remains high during the entire reset cycle.

Figure 3. Expanded Block Diagram

PULSE

SHAPER

CLOCK

DISABLE

(ACTIVE

HIGH)

Q0
Q1
Q2
Q3

UNITS

Q0
Q1
Q2
Q3

TENS

Q0
Q1
Q2
Q3

HUNDREDS

LATCH ENABLE

QUAD

LATCH

QUAD

LATCH

QUAD

LATCH

SCAN

OSCILLATOR

SCANNER

PULSE

GENERATOR

C1A

C1B

MULTIPLEXER

BCD

OUTPUTS

(ACTIVE

HIGH)

(ACTIVE HIGH)

OVERFLOW

DS1

DS2

DS3

(LSD) DIGIT SELECT (MSD)

(ACTIVE LOW)

MOTOROLA CMOS LOGIC DATA

MC14553B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 64808

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A

16 PL

SEATING

PLANE

T

0.25 (0.010)

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.740

0.770

18.80

19.55

0.250

0.270

6.35

6.85

0.145

0.175

3.69

4.44

0.015

0.021

0.39

0.53

0.040

0.70

1.02

1.77

0.100 BSC

2.54 BSC

0.050 BSC

1.27 BSC

0.008

0.015

0.21

0.38

0.110

0.130

2.80

3.30

0.295

0.305

7.50

7.74

0.020

0.040

0.51

1.01

L SUFFIX

CERAMIC DIP PACKAGE

CASE 62010

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC
BODY.

A

B

T

SEATING
PLANE

16 PL

0.25 (0.010)

16 PL

0.25 (0.010)

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.750

0.785

19.05

19.93

0.240

0.295

6.10

7.49

0.200

5.08

0.015

0.020

0.39

0.50

0.050 BSC

1.27 BSC

0.055

0.065

1.40

1.65

0.100 BSC

2.54 BSC

0.008

0.015

0.21

0.38

0.125

0.170

3.18

4.31

0.300 BSC

7.62 BSC

0.020

0.040

0.51

1.01

MOTOROLA CMOS LOGIC DATA

MC14553B
8

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G02

ISSUE A

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

10.15

10.45

0.400

0.411

7.40

7.60

0.292

0.299

2.35

2.65

0.093

0.104

0.35

0.49

0.014

0.019

0.50

0.90

0.020

0.035

1.27 BSC

0.050 BSC

0.25

0.32

0.010

0.012

0.10

0.25

0.004

0.009

10.05

10.55

0.395

0.415

0.25

0.75

0.010

0.029

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

A

B

14X

16X

SEATING
PLANE

T

0.010 (0.25)

X 45

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and

are registered

trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC14553B/D

*MC14553B/D*

Part Number MC14553B