MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 7

Motorola, Inc. 1997

2/97

Octal 3-State Noninverting

Buffer/Line Driver/

Line Receiver

HighPerformance SiliconGate CMOS

The MC54/74HC244A is identical in pinout to the LS244. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed to be

used with 3state memory address drivers, clock drivers, and other
busoriented systems. The device has noninverting outputs and two
activelow output enables.

The HC244A is similar in function to the HC240A and HC241A.

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard
No. 7A

Chip Complexity: 136 FETs or 34 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING
OUTPUTS

PIN 20 = VCC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A

ENABLE B

MC54/74HC244A

PIN ASSIGNMENT

YB4

ENABLE A

GND

YB1

YB2

YB3

YA2

YA1

ENABLE B

VCC

YA4

YA3

FUNCTION TABLE

Inputs

Outputs

Enable A,
Enable B

A, B

YA, YB

Z = high impedance

DW SUFFIX

SOIC PACKAGE

CASE 751D04

N SUFFIX

PLASTIC PACKAGE

CASE 73803

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT

Ceramic
Plastic
SOIC
SSOP
TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E02

J SUFFIX

CERAMIC PACKAGE

CASE 73203

SD SUFFIX

SSOP PACKAGE

CASE 940C03

MC54/74HC244A

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic or Ceramic DIP

SOIC Package

SSOP or TSSOP Package

ÎÎÎÎÎÎ

ÎÎÎÎ

750
500
450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

ÎÎÎÎ

65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎ

260
300

ÎÎÎ

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

Derating -- Plastic DIP: 10 mW/

C from 65

to 125

Ceramic DIP: 10 mW/

C from 100

to 125

SOIC Package: 7 mW/

C from 65

to 125

SSOP or TSSOP Package: 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

ÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time

VCC = 2.0 V

(Figure 1)

VCC = 4.5 V
VCC = 6.0 V

ÎÎÎ

0
0
0

ÎÎÎ

1000

500
400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VCC

ÎÎÎ

ÎÎ

ÎÎÎ

 55 to

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vout = VCC 0.1 V
|Iout|

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

1.5
2.1

3.15

4.2

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Input
Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V
|Iout|

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.5
0.9

1.35

1.8

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.5
0.9

1.35

1.8

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.5
0.9

1.35

1.8

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Minimum HighLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH
|Iout|

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

1.9
4.4
5.9

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

1.9
4.4
5.9

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

|Iout|

2.4 mA

|Iout|

6.0 mA

|Iout|

7.8 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

2.48
3.98
5.48

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.34
3.84
5.34

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.2
3.7
5.2

ÎÎÎ

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND

(Vin or Vout)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC244A

HighSpeed CMOS Logic Data
DL129 -- Rev 6

MOTOROLA

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum LowLevel Output
Voltage

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIL
|Iout|

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.1
0.1
0.1

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.1
0.1
0.1

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIL

|Iout|

2.4 mA

|Iout|

6.0 mA

|Iout|

7.8 mA

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.26
0.26
0.26

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.33
0.33
0.33

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

0.4
0.4
0.4

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

0.1

ÎÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum ThreeState Leakage
Current

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Output in HighImpedance State

Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

5.0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply
Current (per Package)

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND
Iout = 0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

4.0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

160

ÎÎÎ

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High

Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS

(CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

b l

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

U i

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

96
50
18
15

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

115

60
23
20

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

135

70
27
23

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

110

60
22
19

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

140

70
28
24

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

165

80
33
28

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

110

60
22
19

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

140

70
28
24

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

165

80
33
28

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

2.0
3.0
4.5
6.0

ÎÎÎ

ÎÎ

ÎÎÎ

60
23
12
10

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

75
27
15
13

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

90
32
18
15

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum ThreeState Output Capacitance (Output in
HighImpedance State)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎ

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High

Speed CMOS Data Book (DL129/D).

B ff )*

Typical @ 25

C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Buffer)*

* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola HighSpeed CMOS Data Book (DL129/D).

MC54/74HC244A

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 73203

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 73803

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE

POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

23.88

25.15

0.940

0.990

6.60

7.49

0.260

0.295

3.81

5.08

0.150

0.200

0.38

0.56

0.015

0.022

1.40

1.65

0.055

0.065

2.54 BSC

0.100 BSC

0.51

1.27

0.020

0.050

0.20

0.30

0.008

0.012

3.18

4.06

0.125

0.160

7.62 BSC

0.300 BSC

0.25

1.02

0.010

0.040

SEATING
PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

20 PL

0.25 (0.010)

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

25.66

27.17

1.010

1.070

6.10

6.60

0.240

0.260

3.81

4.57

0.150

0.180

0.39

0.55

0.015

0.022

2.54 BSC

0.100 BSC

0.21

0.38

0.008

0.015

2.80

3.55

0.110

0.140

7.62 BSC

0.300 BSC

0.51

1.01

0.020

0.040

1.27

1.77

0.050

0.070

A

SEATING
PLANE

20 PL

T

0.25 (0.010)

1.27 BSC

0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

A

B

0.010 (0.25)

20X

0.010 (0.25)

10X

18X

T

SEATING
PLANE

X 45

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

12.65

12.95

0.499

0.510

7.40

7.60

0.292

0.299

2.35

2.65

0.093

0.104

0.35

0.49

0.014

0.019

0.50

0.90

0.020

0.035

1.27 BSC

0.050 BSC

0.25

0.32

0.010

0.012

0.10

0.25

0.004

0.009

10.05

10.55

0.395

0.415

0.25

0.75

0.010

0.029

MC54/74HC244A

HighSpeed CMOS Logic Data
DL129 -- Rev 6

MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E02

ISSUE A

DIM

MIN

MAX

MIN

MAX

INCHES

6.60

0.260

MILLIMETERS

4.30

4.50

0.169

0.177

1.20

0.047

0.05

0.15

0.002

0.006

0.50

0.75

0.020

0.030

0.65 BSC

0.026 BSC

0.27

0.37

0.011

0.015

0.09

0.20

0.004

0.008

0.09

0.16

0.004

0.006

0.19

0.30

0.007

0.012

0.19

0.25

0.007

0.010

6.40 BSC

0.252 BSC

0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE W.

ÍÍÍÍ

PIN 1
IDENT

T

0.100 (0.004)

SECTION NN

J J1

W

SEATING
PLANE

V

U

0.10 (0.004)

20X REF

L/2

0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40

0.252

0.15 (0.006) T

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940C03

ISSUE B

20X REF

0.12 (0.005)

L/2

PIN 1
IDENT

0.20 (0.008)

V

U

0.076 (0.003)

T

SEATING
PLANE

DETAIL E

0.25 (0.010)

ÇÇÇ

ÉÉÉ

SECTION NN

DIM

MIN

MAX

MIN

MAX

INCHES

7.07

7.33

0.278

0.288

MILLIMETERS

5.20

5.38

0.205

0.212

1.73

1.99

0.068

0.078

0.05

0.21

0.002

0.008

0.63

0.95

0.024

0.037

0.65 BSC

0.026 BSC

0.59

0.75

0.023

0.030

0.09

0.20

0.003

0.008

0.09

0.16

0.003

0.006

0.25

0.38

0.010

0.015

0.25

0.33

0.010

0.013

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE

ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE W.

7.65

7.90

0.301

0.311

DETAIL E

W

MC54/74HC244A

MOTOROLA

HighSpeed CMOS Logic Data

DL129 -- Rev 6

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MC74HC244A/D

Part Number 74HC244