Sep. 1999 , Rev.2.0

MITSUBISHI LSIs

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM

Stacked-MCP (Multi Chip Package)

M6MGB/T162S4BVP

DESCRIPTION

The MITSUBISHI M6MGB/T162S4BVP is a Stacked Multi
Chip Package (S-MCP) that contents 16M-bits flash memory
and 4M-bits Static RAM in a 48-pin TSOP (TYPE-I).

16M-bits Flash memory is a 1048576 words, 3.3V-only, and
high performance non-volatile memory fabricated by CMOS
technology for the peripheral circuit and DINOR(DIvided
bit-line NOR) architecture for the memory cell.
4M-bits SRAM is a 262144words unsynchronous SRAM
fabricated by silicon-gate CMOS technology.

M6MGB/T162S4BVP is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .

· Access time
Flash Memory 90ns (Max.)
SRAM 85ns (Max.)
· Supply voltage Vcc=2.7 ~ 3.6V
· Ambient temperature
W version Ta=-20 ~ 85

· Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch

APPLICATION

FEATURES

Mobile communication products

2
3

16
17

22
23

43
42

37
36

30
29

14.0 mm

PIN CONFIGURATION (TOP VIEW)

F-VCC

:Vcc for Flash

GND

:GND for Flash SRAM

S-VCC

:Vcc for SRAM

S-A-1

:Address for SRAM

A18-A19

:Address for Flash

F-CE#

:Flash Chip Enable

WE#

:Flash/SRAM Write Enable

DQ0-DQ15

:Data I/O

F-WP#

:Flash Write Protect

F-RP#

:Flash Reset Power Down

S-CE

:SRAM Chip Enable

F-RY/BY#

:Flash Ready /Busy

OE#

:Flash/SRAM Output Enable

NC:Non Connection

10.0 mm

A16

F-CE#

DQ0

GND

OE#

DQ8

DQ1

DQ9

DQ2

F-VCC

GND

DQ15

DQ10

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

S-A-1

A18

A17

F-RY/BY#

A11

A10

A15

A13
A12

A14

F-RP#

A7
A6
A5

WE#

F-WP#

A19

S-VCC

S-CE

A0-A17

:Flash/SRAM common Address

Sep. 1999 , Rev.2.0

MITSUBISHI LSIs

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM

Stacked-MCP (Multi Chip Package)

M6MGB/T162S4BVP

BLOCK DIAGRAM

DATA INPUTS/OUTPUTS

MULTIPLEXER

INPUT/OUTPUT

BUFFERS

WSM

16Mb Flash Memory

X-DECODER

Y-DECODER

Y-GATE / SENSE AMP.

F-CE#
OE#
WE#

F-VCC(3.3V)

GND (0V)

F-WP#
F-RP#

CUI

STATUS / ID REGISTER

128 WORD PAGE BUFFER

Main Block 32KW

F-RY/BY#

READY/BUSY OUTPUT

ADDRESS

INPUTS

CHIP ENABLE INPUT

OUTPUT ENABLE INPUT

WRITE ENABLE INPUT

WRITE PROTECT INPUT

RESET/POWER DOWN INPUT

Main Block 32KW

Bank(II)

Parameter Block5 16KW

Parameter Block6 16KW

Boot Block 16KW

Parameter Block3 16KW

Parameter Block4 16KW

Parameter Block1 16KW

Parameter Block2 16KW

Bank(I)

Parameter Block7 16KW

WSM

ADDRESS INPUT BUFFER

ROW DECODER

S-CE

WE#

OE#

524288 WORD x

8 BITS

CLOCK

GENERATOR

SENSE AMP.

DQ 7

DQ 0

S-VCC

GND

OUTPUT BUFFER

DATAINPUT

BUFFER

S-A

-1

4Mb SRAM

Sep. 1999 , Rev.2.0

MITSUBISHI LSIs

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM

Stacked-MCP (Multi Chip Package)

M6MGB/T162S4BVP

DESCRIPTION

The Flash Memory of M6MGB/T162S4BVP is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating

BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank

while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and

personal computing, and communication products. The Flash Memory of M6MGB/T162S4BVP is fabricated by CMOS technology for the

peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells.

FEATURES

Boot Block
M6MGB162S4BVP Bottom Boot
M6MGT162S4BVP Top Boot

Other Functions
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)

Organization 1048,576 word x 16bit

Supply voltage

................................

= 2.7~3.6V

Access time 90ns (Max.)

Power Dissipation
Read 54 mW (Max. at 5MHz)
(After Automatic Power saving) 0.33

W (typ.)

Program/Erase 126 mW (Max.)
Standby 0.33

W (typ.)

Deep power down mode 0.33

W (typ.)

Auto program for Bank(I)
Program Time 4ms (typ.)
Program Unit
(Byte Program) 1word
(Page Program) 128word
Auto program for Bank(II)
Program Time 4ms (typ.)
Program Unit 128word
Auto Erase
Erase time 40 ms (typ.)
Erase Unit
Bank(I) Boot Block 16Kword x 1
Parameter Block 16Kword x 7
Bank(II) Main Block 32Kword x 28

Program/Erase cycles 100Kcycles

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1. Flash Memory

Sep. 1999 , Rev.2.0

MITSUBISHI LSIs

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM

Stacked-MCP (Multi Chip Package)

M6MGB/T162S4BVP

FUNCTION

Deep Power-Down

When F-RP# is at VIL, the device is in the deep powerdown

mode and its power consumption is substantially low. During

read modes, the memory is deselected and the data

input/output are in a high-impedance(High-Z) state. After

return from powerdown, the CUI is reset to Read Array , and

the Status Register is cleared to value 80H.

During block erase or program modes, F-RP# low will abort

either operation. Memory array data of the block being altered

become invalid.

The Flash Memory of M6MGB/T162S4BVP includes on-chip

program/erase control circuitry. The Write State Machine (WSM)

controls block erase and byte/page program operations.

Operational modes are selected by the commands written to the

Command User Interface (CUI). The Status Register indicates the

status of the WSM and when the WSM successfully completes the

desired program or block erase operation.

A Deep Powerdown mode is enabled when the F-RP# pin is at

GND, minimizing power consumption.

Read

The Flash Memory of M6MGB/T162S4BVP has three read modes,

which accesses to the memory array, the Device Identifier and the

Status Register. The appropriate read command are required to

be written to the CUI. Upon initial device powerup or after exit

from deep powerdown, the Flash Memory automatically resets to

read array mode. In the read array mode, low level input to F-CE#

and OE#, high level input to WE# and F-RP#, and address signals

to the address inputs ( A19-A0:Word Mode) output the data of the

addressed location to the data input/output ( D15-D0:Word Mode).

Write

Writes to the CUI enables reading of memory array data, device

identifiers and reading and clearing of the Status Register. They

also enable block erase and program. The CUI is written by

bringing WE# to low level, while F-CE# is at low level and OE# is

at high level. Address and data are latched on the earlier rising

edge of WE# and F-CE#. Standard micro-processor write timings

are used.

Standby
When F-CE# is at VIH, the device is in the standby mode and
its power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.

Alternating Background Operation (BGO)

The Flash Memory of M6MGB/T162S4BVP allows to read array

from one bank while the other bank operates in software

command write cycling or the erasing / programming operation in

the background. Read array operation with the other bank in BGO

is performed by changing the bank address without any additional

command. When the bank address points the bank in software

command write cycling or the erasing / programming operation,

the data is read out from the status register. The access time with

BGO is the same as the normal read operation.

Output Disable

When OE# is at VIH, output from the devices is disabled. Data

input/output are in a high-impedance(High-Z) state.

Automatic Power-Saving (APS)

The Automatic Power-Saving minimizes the power

consumption during read mode. The device automatically

turns to this mode when any addresses or F-CE# isn't

changed more than 200ns after the last alternation. The

power consumption becomes the same as the stand-by

mode. While in this mode, the output data is latched and can

be read out. New data is read out correctly when addresses

are changed.

Sep. 1999 , Rev.2.0

MITSUBISHI LSIs

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM

Stacked-MCP (Multi Chip Package)

M6MGB/T162S4BVP

SOFTWARE COMMAND DEFINITIONS

The device operations are selected by writing specific software

command into the Command User Interface.

Read Array Command (FFH)

The device is in Read Array mode on initial device power up and

after exit from deep powerdown, or by writing FFH to the

Command User Interface. After starting the internal operation the

device is set to the read status register mode automatically.

Read Device Identifier Command (90H)

It can normally read device identifier codes when Read Device

Identifier Code Command(90H) is written to the command latch.

Following the command write, the manufacturer code and the

device code can be read from address 0000H and 0001H,

respectively.

Read Status Register Command (70H)

The Status Register is read after writing the Read Status Register

command of 70H to the Command User Interface. Also, after

starting the internal operation the device is set to the Read Status

The contents of Status Register are latched on the later falling

edge of OE# or F-CE#. So F-CE# or OE# must be toggled every

status read.

Clear Status Register Command (50H)

The Erase Status, Program Status and Block Status bits are set to

"1"s by the Write State Machine and can only be reset by the Clear

Status Register command of 50H. These bits indicates various

failure conditions.

Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.

Program Commands

A)Word/Byte Program (40H)
Word program is executed by a two-command sequence. The
Word Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word Program
Command is Valid for only Bank(I).

DATA PROTECTION

The Flash Memory of M6MGB/T162S4BVP provides selectable
block locking of memory blocks. Each block has an associated
nonvolatile lock-bit which determines the lock status of the block.
In addition, the Flash Memory has a master Write Protect pin
(F-WP#) which prevents any modifications to memory blocks
whose lock-bits are set to "0", when F-WP# is low. When F-WP#
is high, all blocks can be programmed or erased regardless of
the state of the lock-bits, and the lock-bits are cleared to "1" by
erase. See the BLOCK LOCKING table on P.9 for details.

Power Supply Voltage
When the power supply voltage (F-VCC) is less than V

LKO,

Low

Lock-Out voltage, the device is set to the Read-only mode.

Regarding DC electrical characteristics of V

LKO,

see P.10.

A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time F-Vcc reaches
F-Vccmin (2.7V).
During power up, F-RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.

MEMORY ORGANIZATION
The Flash Memory of M6MGB/T162S4BVP has one 16Kword boot
block, seven 16Kword parameter blocks, for Bank(I) and
twenty-eight 32Kword main blocks for Bank(II). A block is erased
independently of other blocks in the array.

Suspend/Resume Command (B0H/D0H)

Writing the Suspend command of B0H during block erase

operation interrupts the block erase operation and allows read out

from another block of memory. Writing the Suspend command of

B0H during program operation interrupts the program operation

and allows read out from another block of memory. The Bank

address is required when writing the Suspend/Resume Command.

The device continues to output Status Register data when read,

after the Suspend command is written to it. Polling the WSM

Status and Suspend Status bits will determine when the erase

operation or program operation has been suspended. At this

point, writing of the Read Array command to the CUI enables

reading data from blocks other than that which is suspended.

When the Resume command of D0H is written to the CUI,

the WSM will continue with the erase or program processes.

B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words/256bytes of data. Writing of 41H initiates the page
program operation for the Data area. From 2nd cycle to
129th cycle, write data must be serially inputted. Address A6-A0
have to be incremented from 00H to 7FH. After completion of data
loading, the WSM controls the program pulse application and verify
operation.

C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 128word can be loaded to the page
buffer by this two-command sequence. On the other hand, all of
the loaded data to the page buffer is programed simultaneously
by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
This command is valid for only Bank(I) alike Word Program.

Clear Page Buffer Command (55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.

Part Number M6MGB162S4BVP