MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Ver. 1.1
MITSUBISHI
ELECTRIC
NC : NO CONNECTION
DESCRIPTION
FEATURES
Type name
Access
time
(max)
Active
(max)
stand-by
(max)
Power supply current
The M5M51008DP,FP,VP,RV,KV are a 1048576-bit CMOS static
RAM organized as 131072 word by 8-bit which are fabricated using
high-performance quadruple-polysilicon and double metal CMOS
technology. The use of thin film transistor (TFT) load cells and
CMOS periphery result in a high density and low power static
RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008DVP,RV,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD). Two types of devices are available.
M5M51008DVP(normal lead bend type package),
M5M51008DRV(reverse lead bend type package).Using both types
of devices, it becomes very easy to design a printed circuit board.
Package
APPLICATION
Small capacity memory units
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S
1
,S
2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
M5M51008DFP,VP,RV,KV-55H
55ns
15mA
70ns
20µA
(1MHz)
M5M51008DFP,VP,RV,KV-70H
16
15
14
13
1
12
11
10
9
8
7
6
5
4
3
2
PIN CONFIGURATION (TOP VIEW)
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
V
CC
A
15
S
2
W
A
13
A
8
A
9
A
11
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
A
11
A
9
A
8
A
13
W
S
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
GND
DQ
3
DQ
2
DQ
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
11
A
2
A
0
OE
A
1
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
17
18
19
20
32
M5M51008DVP,KV
A
14
A
16
NC
V
CC
A
15
S
2
W
A
13
A
8
A
9
DQ
1
DQ
2
DQ
3
GND
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
S
1
A
10
A
12
21
22
23
24
25
26
27
28
29
30
31
Outline 32P2M-A(FP)
Outline 32P3H-E(VP), 32P3K-B(KV)
ADDRESS
INPUT
CHIP SELECT
INPUT
WRITE CONTROL
INPUT
ADDRESS
INPUTS
OUTPUT ENABLE
INPUT
ADDRESS
INPUT
CHIP SELECT
INPUT
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
M5M51008DRV
Outline 32P3H-F(RV)
(Vcc=5.5V)
(1MHz)
1
M5M51008DFP
············ 32pin 525mil SOP
M5M51008DVP,RV ············ 32pin 8 X 20 mm
TSOP
M5M51008DKV
············ 32pin 8 X 13.4 mm
TSOP
2
2
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Ver. 1.1
MITSUBISHI
ELECTRIC
FUNCTION
BLOCK DIAGRAM
The operation mode of the M5M51008D series are determined by
a combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S
1
and the high level S
2
. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
1
or
S
2
,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
When setting S
1
at a high level or S
2
at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
1
and S
2
. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
S
1
S
2
W
OE
Mode
DQ
I
CC
L
L
H
H
H
H
L
H
Non selection
Write
Read
High-impedance
Din
Dout
Active
Stand-by
Non selection High-impedance
High-impedance
Active
Active
Stand-by
FUNCTION TABLE
L
H
L
X
H
X
X
X
X
L
X
X
CLOCK
GENERATOR
131072 WORDS
X 8 BITS
(512 ROWS
X128 COLUMNS
X 16BLOCKS)
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
5
30
6
32
8
29
22
30
24
32
16
24
A3
A2
A5
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
A1
A0
A10
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
W
S1
S2
OE
V
CC
GND
(0V)
* Pin numbers inside dotted line show those of TSOP
*
*
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
CHIP
SELECT
INPUTS
OUTPUT
ENABLE
INPUT
ADDRESS
INPUTS
A4
2
7
10
3
4
5
6
7
10
9
11
12
13
14
15
18
17
2
31
2
3
4
28
27
26
1
25
20
19
11
12
31
23
16
8
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Ver. 1.1
MITSUBISHI
ELECTRIC
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
Symbol
Parameter
Test conditions
pF
pF
Unit
Max
10
Typ
Min
Limits
Input capacitance
Output capacitance
C
I
C
O
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Unit
V
V
V
mW
°C
°C
Conditions
With respect to GND
Ta=25°C
700
0~70
65~150
Ratings
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
DC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
V
V
V
Max
Typ
Limits
Min
Test conditions
Unit
V
µA
0.3*~7
0.3*~Vcc + 0.3
(Ta=0~70°C, Vcc=5V±10% unless otherwise noted)
0~Vcc
* 3.0V in case of AC ( Pulse width
50ns )
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
mA
* 3.0V in case of AC ( Pulse width
50ns )
µA
µA
mA
V
Vcc + 0.3
0.8
2.2
0.3*
2.4
3
Stand-by current
0.4
±1
Active supply current
(AC, MOS level)
Active supply current
(AC, TTL level)
Vcc 0.5
±1
80
V
IH
V
IL
V
OH
V
OL
I
I
I
O
I
CC1
I
CC2
I
CC3
I
CC4
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
Output current in off-state
Stand-by current
I
OH
=
1.0mA
I
OH
=
0.1mA
I
OL
=2mA
V
I
=0~Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0~V
CC
S
1
=V
IL
,S
2
=V
IH
,
other inputs=V
IH
or V
IL
Output-open(duty 100%)
1) S
2
0.2V,
other inputs=0~V
CC
2) S
1
V
CC
0.2V,
S
2
V
CC
0.2V,
other inputs=0~V
CC
S
1
=V
IH
or S
2
=V
IL
,
other inputs=0~V
CC
~25°C
~40°C
~70°C
-H
2
6
20
mA
15
1MHz
S
1
0.2V, S
2
VCC0.2V
other inputs
0.2V or
VCC0.2V
Output-open(duty 100%)
85
15
70ns
55ns
70
70
1MHz
70ns
55ns
V
O
=GND,V
O
=25mVrms, f=1MHz
FP,VP,RV,KV
FP,VP,RV,KV
V
I
=GND, V
I
=25mVrms, f=1MHz
8
3
4
5
34
37
39
42
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Ver. 1.1
MITSUBISHI
ELECTRIC
(2) READ CYCLE
(3) WRITE CYCLE
Symbol
Parameter
t
CR
Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
t
a(A)
Limits
AC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, 5V±10% unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
70
70
70
35
25
25
25
70
10
10
5
10
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
25
25
70
50
0
55
55
55
30
0
0
5
5
Input pulse level
V
IH
=2.4V,V
IL
=0.6V (-70H)
V
IH
=3.0V,V
IL
=0.0V (-55H)
Input rise and fall time
5ns
Reference level
V
OH
=V
OL
=1.5V
Output loads
Fig.1, C
L
=100pF (-70H)
C
L
=30pF (-55H)
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
...............
.....................
......
................
Fig.1 Output load
Min
Max
-70H
Max
Min
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
-70H
C
L
( Including scope
and JIG )
990
1.8k
V
CC
DQ
20
20
55
45
0
50
50
50
25
0
0
5
5
Max
Min
-55H
55
55
55
30
20
20
20
55
5
5
5
5
Min
Max
-55H
4
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Ver. 1.1
MITSUBISHI
ELECTRIC
t
en (W)
Read cycle
Write cycle (W control mode)
(4) TIMING DIAGRAMS
DATA VALID
(Note 3)
(Note 3)
t
a(A)
t
a (S1)
t
v (A)
t
a (S2)
t
en (S2)
t
dis (S1)
t
dis (S2)
t
a (OE)
t
en (OE)
t
dis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
t
CR
t
h (D)
t
su (D)
DQ
1~8
S
1
t
su (S1)
S
2
OE
t
su (S2)
t
su (A-WH)
t
en(OE)
t
dis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
W
t
w (W)
t
rec (W)
t
su (A)
t
dis (W)
t
CW
t
en (S1)
W = "H" level
A
0~16
DQ
1~8
S
1
S
2
OE
A
0~16
STABLE
DATA IN
5
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