MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

DESCRIPTION

The MITSUBISHI Mobile FLASH M5M29GB/T161BWG are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with

alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in

one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for

mobile and personal computing, and communication products. The M5M29GB/T161BWG are fabricated by CMOS technology for the

peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 6x8-balls CSP (0.75mm ball

pitch) .

FEATURES

PIN CONFIGURATION (TOP VIEW)

APPLICATION

Digital Cellular Phone
Telecommunication
Mobile Computing Machine
PDA (Personal Digital Assistance)
Car Navigation System
Video Game Machine

Boot Block
M5M29GB161BWG Bottom Boot
M5M29GT161BWG Top Boot

Other Functions
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)

Package
7mm x 8.5mm CSP (Chip Scale Package)
- 6 x 8 balls, 0.75mm ball pitch

........................
........................

NC : NO CONNECTION

INDEX

M5M29GB/T161BWG

A13

A11

A14

A15

A12

A10

WE#

A16

GND

D15

D13

WP2#

RP#

WP1#

A18

D11

D12

VCC

D10

OE#

GND

CE#

A17

D14

8.5mm

7.0mm

CSP(0.75mm ball pitch):48FJA

16-bit version

A19

Organization 1048,576 word x 16bit
(M5M29GB/T161BWG)

Supply voltage

................................

= 2.7~3.6V

Access time 90ns (Max.)

Power Dissipation
Read 54 mW (Max. at 5MHz)
(After Automatic Power saving) 0.33

W (typ.)

Program/Erase 126 mW (Max.)
Standby 0.33

W (typ.)

Deep power down mode 0.33

W (typ.)

Auto program for Bank(I)
Program Time 4ms (typ.)
Program Unit
(Byte Program) 1word
(Page Program) 128word
Auto program for Bank(II)
Program Time 4ms (typ.)
Program Unit 128word
Auto Erase
Erase time 40 ms (typ.)
Erase Unit
Bank(I) Boot Block 16Kword x 1
Parameter Block 16Kword x 7
Bank(II) Main Block 32Kword x 28

Program/Erase cycles 100Kcycles

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MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

FUNCTION

Deep Power-Down

When RP# is at VIL, the device is in the deep powerdown

mode and its power consumption is substantially low. During

read modes, the memory is deselected and the data

input/output are in a high-impedance(High-Z) state. After

return from powerdown, the CUI is reset to Read Array , and

the Status Register is cleared to value 80H.

During block erase or program modes, RP# low will abort

either operation. Memory array data of the block being altered

become invalid.

The M5M29GB/T161BWG includes on-chip program/erase control

circuitry. The Write State Machine (WSM) controls block erase

and byte/page program operations. Operational modes are

selected by the commands written to the Command User Interface

(CUI). The Status Register indicates the status of the WSM and

when the WSM successfully completes the desired program or

block erase operation.

A Deep Powerdown mode is enabled when the RP# pin is at GND,

minimizing power consumption.

Read

The M5M29GB/T161BWG has three read modes, which accesses

to the memory array, the Device Identifier and the Status Register.

The appropriate read command are required to be written to the

CUI. Upon initial device powerup or after exit from deep

powerdown, the M5M29GB/T161BWG automatically resets to read

array mode. In the read array mode, low level input to CE# and

OE#, high level input to WE# and RP#, and address signals to the

address inputs (A19-A0:M5M29GB/T161BWG) output the data of

the addressed location to the data input/output

(D15-D0:M5M29GB/T161BWG).

Write

Writes to the CUI enables reading of memory array data, device

identifiers and reading and clearing of the Status Register. They

also enable block erase and program. The CUI is written by

bringing WE# to low level, while CE# is at low level and OE# is at

high level. Address and data are latched on the earlier rising edge

of WE# and CE#. Standard micro-processor write timings are

used.

Standby
When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.

Alternating Background Operation (BGO)

The M5M29GB/T161BWG allows to read array from one bank

while the other bank operates in software command write cycling

or the erasing / programming operation in the background. Read

array operation with the other bank in BGO is performed by

changing the bank address without any additional command.

When the bank address points the bank in software command

write cycling or the erasing / programming operation, the data is

read out from the status register. The access time with BGO is the

same as the normal read operation.

Output Disable

When OE# is at VIH, output from the devices is disabled. Data

input/output are in a high-impedance(High-Z) state.

Automatic Power-Saving (APS)

The Automatic Power-Saving minimizes the power

consumption during read mode. The device automatically

turns to this mode when any addresses or CE# isn't changed

more than 200ns after the last alternation. The power

consumption becomes the same as the stand-by mode. While

in this mode, the output data is latched and can be read out.

New data is read out correctly when addresses are changed.

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

SOFTWARE COMMAND DEFINITIONS

The device operations are selected by writing specific software

command into the Command User Interface.

Read Array Command (FFH)

The device is in Read Array mode on initial device power up and

after exit from deep powerdown, or by writing FFH to the

Command User Interface. After starting the internal operation the

device is set to the read status register mode automatically.

Read Device Identifier Command (90H)

It can normally read device identifier codes when Read Device

Identifier Code Command(90H) is written to the command latch.

Following the command write, the manufacturer code and the

device code can be read from address 0000H and 0001H,

respectively.

Read Status Register Command (70H)

The Status Register is read after writing the Read Status Register

command of 70H to the Command User Interface. Also, after

starting the internal operation the device is set to the Read Status

The contents of Status Register are latched on the later falling

edge of OE# or CE#. So CE# or OE# must be toggled every status

read.

Clear Status Register Command (50H)

The Erase Status, Program Status and Block Status bits are set to

"1"s by the Write State Machine and can only be reset by the Clear

Status Register command of 50H. These bits indicates various

failure conditions.

Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.

Program Commands

A)Word Program (40H)
Word program is executed by a two-command sequence. The
Word Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word Program
Command is Valid for only Bank(I).

DATA PROTECTION

The M5M29GB/T161BWG provides selectable block locking of
memory blocks. Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In addition, the
M5M29GB/T161BWG have a master Write Protect pin (WP1# &
WP2#) which prevents any modifications to memory blocks whose
lock-bits are set to "0", when WP1# or WP2# is low. When WP1#
& WP2# are high , all blocks can be programmed or erased
regardless of the state of the lock-bits, and the lock-bits are
cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for
details.

Power Supply Voltage
When the power supply voltage (Vcc) is less than V

LKO,

Low V

Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of V

LKO,

see P.9

A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (2.7V).
During power up, RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.

MEMORY ORGANIZATION
The M5M29GB/T161BWG has one 16Kword boot block, seven
16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword
main blocks for Bank(II). A block is erased independently of other
blocks in the array.

Suspend/Resume Command (B0H/D0H)

Writing the Suspend command of B0H during block erase

operation interrupts the block erase operation and allows read out

from another block of memory. Writing the Suspend command of

B0H during program operation interrupts the program operation

and allows read out from another block of memory. The Bank

address is required when writing the Suspend/Resume Command.

The device continues to output Status Register data when read,

after the Suspend command is written to it. Polling the WSM

Status and Suspend Status bits will determine when the erase

operation or program operation has been suspended. At this

point, writing of the Read Array command to the CUI enables

reading data from blocks other than that which is suspended.

When the Resume command of D0H is written to the CUI,

the WSM will continue with the erase or program processes.

B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words of data. Writing of 41H initiates the page program
operation for the Data area. From 2nd cycle to 129th cycle , write
data must be serially inputted. Address A6-A0 have to be
incremented from 00H to 7FH. After completion of data loading, the
WSM controls the program pulse application and verify operation.

C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 128word can be loaded to the page
buffer by this two-command sequence. On the other hand, all of
the loaded data to the page buffer is programed simultaneously
by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
This command is valid for only Bank(I) alike Word Program.

Clear Page Buffer Command (55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

M5M29GT161BWG Memory Map

BANK(I)

BANK(II)

16Kword BOOT BLOCK 35

16Kword PARAMETER BLOCK 34

32Kword MAIN BLOCK 27

32Kword MAIN BLOCK 26

32Kword MAIN BLOCK 25

32Kword MAIN BLOCK 24

32Kword MAIN BLOCK 23

32Kword MAIN BLOCK 22

32Kword MAIN BLOCK 21

32Kword MAIN BLOCK 20

32Kword MAIN BLOCK 19

32Kword MAIN BLOCK 18

32Kword MAIN BLOCK 17

32Kword MAIN BLOCK 16

32Kword MAIN BLOCK 15

32Kword MAIN BLOCK 14

32Kword MAIN BLOCK 13

32Kword MAIN BLOCK 12

32Kword MAIN BLOCK 11

32Kword MAIN BLOCK 10

32Kword MAIN BLOCK 9

32Kword MAIN BLOCK 8

32Kword MAIN BLOCK 7

32Kword MAIN BLOCK 6

32Kword MAIN BLOCK 5

32Kword MAIN BLOCK 4

32Kword MAIN BLOCK 3

32Kword MAIN BLOCK 2

32Kword MAIN BLOCK 1

32Kword MAIN BLOCK 0

16Kword PARAMETER BLOCK 33

16Kword PARAMETER BLOCK 32

16Kword PARAMETER BLOCK 31

16Kword PARAMETER BLOCK 30

16Kword PARAMETER BLOCK 29

16Kword PARAMETER BLOCK 28

MEMORY ORGANIZATION

-A

(M5M29GB161BWG)

M5M29GB161BWG Memory Map

32Kword MAIN BLOCK 35

32Kword MAIN BLOCK 34

32Kword MAIN BLOCK 33

32Kword MAIN BLOCK 32

32Kword MAIN BLOCK 31

32Kword MAIN BLOCK 30

32Kword MAIN BLOCK 29

32Kword MAIN BLOCK 28

32Kword MAIN BLOCK 27

32Kword MAIN BLOCK 26

32Kword MAIN BLOCK 25

32Kword MAIN BLOCK 24

32Kword MAIN BLOCK 23

32Kword MAIN BLOCK 22

BANK(II)

32Kword MAIN BLOCK 21

32Kword MAIN BLOCK 20

32Kword MAIN BLOCK 19

32Kword MAIN BLOCK 18

32Kword MAIN BLOCK 17

32Kword MAIN BLOCK 16

32Kword MAIN BLOCK 15

32Kword MAIN BLOCK 14

32Kword MAIN BLOCK 13

32Kword MAIN BLOCK 12

32Kword MAIN BLOCK 11

32Kword MAIN BLOCK 10

32Kword MAIN BLOCK 9

32Kword MAIN BLOCK 8

BANK(I)

16Kword PARAMETER BLOCK 1

16Kword BOOT BLOCK 0

16Kword PARAMETER BLOCK 2

16Kword PARAMETER BLOCK 3

16Kword PARAMETER BLOCK 4

16Kword PARAMETER BLOCK 5

16Kword PARAMETER BLOCK 6

16Kword PARAMETER BLOCK 7

x16 ( Wordmode)

F8000H-FFFFFH

F0000H-F7FFFH

E8000H-EFFFFH

E0000H-E7FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

A8000H-AFFFFH

A0000H-A7FFFH

98000H-9FFFFH

90000H-97FFFH

00000H-03FFFH

18000H-1BFFFH

14000H-17FFFH

10000H-13FFFH

0C000H-0FFFFH

08000H-0BFFFH

04000H-07FFFH

1C000H-1FFFFH

20000H-27FFFH

28000H-2FFFFH

30000H-37FFFH

38000H-3FFFFH

40000H-47FFFH

48000H-4FFFFH

50000H-57FFFH

58000H-5FFFFH

60000H-67FFFH

68000H-6FFFFH

70000H-77FFFH

78000H-7FFFFH

80000H-87FFFH

88000H-8FFFFH

x16 ( Wordmode)

FC000H-FFFFFH

F8000H-FBFFFH

F4000H-F7FFFH

F0000H-F3FFFH

EC000H-EFFFFH

E8000H-EBFFFH

E4000H-E7FFFH

E0000H-E3FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

00000H-07FFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

38000H-3FFFFH

40000H-47FFFH

48000H-4FFFFH

50000H-57FFFH

58000H-5FFFFH

60000H-67FFFH

68000H-6FFFFH

70000H-77FFFH

78000H-7FFFFH

80000H-87FFFH

88000H-8FFFFH

90000H-97FFFH

98000H-9FFFFH

A0000H-A7FFFH

A8000H-AFFFFH

-A

(M5M29GT161BWG)

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

SOFTWARE COMMAND DEFINITION

Command List

1) Upper byte data (DQ8-DQ15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code
3) Bank = Bank Address (Bank(I) or Bank(II)). A19-A17.
4) SRD = Status Register Data
5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address,WD = Write Data
7) WA0,WAn=Write Address, WD0,WDn=Write Data.
: Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit).
and also A19-A7(Block Address, Page Address) must be valid.
8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid.
9) BA = Block Address : Bank1: A19-A14
Bank2: A19-A15
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.

Read Array

FFH

Write

1st bus cycle

2nd bus cycle

Command

Device Identifier

90H

Write

Read

Read Status Register

70H

Write

SRD

Read

Clear Status Register

50H

Write

Page Program

Write

41H

Block Erase / Confirm
Suspend
Resume

Read Lock Bit Status

Lock Bit Program / Confirm

Erase All Unlocked Blocks

Write

20H

Bank

Write

D0H

Write

B0H

Bank

Write

71H

Write

A7H

77H

D0H

Write

Read

D0H

DQ6

Word Program

Write

40H

Write

WD0

Write

10)

Single Data Load to Page Buffer
Page Buffer to Flash

Write

74H

Write

0EH

Write

D0H

Clear Page Buffer

55H

Write

D0H

Bank

Bank(I)

Bank

WDn

Write

WAn

WA0

3rd ~129th bus cycles (

M5M29GB/T161BWG

)

Address

Mode

Data

Address

Mode

Data

Address

Mode

Data

(DQ15-0)

Bank(I)

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

BLOCK LOCKING

1) DQ

provides Lock Status of each block after writing the Read Lock Status command (71H).

WP1# & WP2# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).
2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and
00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode
to array read mode.

STATUS REGISTER

Status

Erase Status

Program Status

Definition

Symbol

(DQ

)

(DQ

)

Write State Machine Status

(DQ

)

(DQ

)

(DQ

)

(DQ

)

(DQ

)

(DQ

)

"1"

"0"

Ready

Busy

Suspended

Operation in Progress / Completed

Error

Successful

Error

Successful

SR.5

SR.4

SR.7

SR.6

SR.1

SR.0

SR.3

SR.2

Block Status after Program

Reserved

Suspend Status

Error

Successful

*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the
over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.

Reserved

Deep Power Down Mode

Write Protection Provided

Locked

RP#

WP1#

WP2#

Lock

Bit

(Internally)

BANK(I)

Lock Bit

Boot

Parameter

Data

Locked

Note

All Blocks Locked

All Blocks Unlocked

Locked

Unlocked

Locked

Unlocked Unlocked Unlocked

Locked

Unlocked Unlocked

Locked

Unlocked

Locked

Only Parameter Block is Unlocked

BANK(II)

161BWG

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

CAPACITANCE

Symbol

Parameter

Test conditions

Unit

Max

Typ

Min

Limits

Ta = 25

C, f = 1MHz, V

= V

out

= 0V

Input capacitance (Address, Control Pins)

Output capacitance

OUT

1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is V

+0.5V which, during transitions, may overshoot to V

+1.5V for periods <20ns.

ABSOLUTE MAXIMUM RATINGS

Conditions

Parameter

With respect to Ground

Symbol

All input or output voltage except V

cc,

A9,RP#

voltage

Unit

Min

Max

4.6

-0.2

Ambient temperature

Temperature under bias

Storage temperature

stg

-50

-65

125

Output short circuit current

OUT

100

-0.6

4.6

-40

All currents are in RMS unless otherwise noted.
1) Typical values at Vcc=3.3V, Ta=25

2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than V

LKO.

If Vcc is less than V

LKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than V

LKO

, the alteration of memory contents

may occur.

DEVICE IDENTIFIER CODE

The upper data(D

15-8)

is "0".

Code

Manufacturer Code

Pins

Hex. Data

1CH

Device Code (-T161BWG)

A0H

Device Code (-B161BWG)

A1H

DC ELECTRICAL CHARACTERISTICS

(Ta = -40~ 85

C, Vcc = 2.7V ~ 3.6V, unless otherwise noted)

Symbol

Parameter

Max

Typ1)

Limits

Min

Test conditions

Unit

standby current

Output leakage current

OUT

Input leakage current

1.0

deep powerdown current

CC3

program current

= 3.6V, V

, CE# = RP# =WP# = V

CC4

erase current

= 3.6V, V

, CE# = RP# =WP# = V

Output high voltage

Output low voltage

= 4.0mA

0.45

Vcc+0.5

Input high voltage

2.0

0.8

Input low voltage

0.5

OH1

= 2.0mA

0.85Vcc

OH2

= 100

Vcc0.4

LKO

Low V

Lock-Out voltage 2)

1.5

2.2

CC5

suspend current

200

= 3.6V, V

, CE# = RP# =WP# = V

SB2

= 3.6V, V

=GND or V

CE# = RP# = WP# = V

0.3V

0.1

CC1

read current for Word or Byte

= 3.6V, V

, CE# = V

RP#=OE#=V

, I

OUT

= 0mA

SB1

= 3.6V, V

, CE# = RP# =WP# = V

200

CC2

Write current for Word or Byte

= 3.6V,V

, CE# =WE#= V

RP#=OE#=V

= 3.6V, V

, RP# = V

SB3

0.1

SB4

= 3.6V, V

=GND or V

, RP# =GND

0.3V

5MHz

1MHz

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

Read-Only Mode

AC ELECTRICAL CHARACTERISTICS

(Ta = -40 ~85

C, Vcc = 2.7V ~3.6V)

Write Mode (WE# control)

AC ELECTRICAL CHARACTERISTICS

(Ta = -40 ~85

C, Vcc = 2.7V ~3.6V)

Timing measurements are made under AC waveforms for read operations.

Symbol

Parameter

Limits

a (AD)

Address access time

AVQV

CLZ

Chip enable to output in low-Z

ELQX

a (CE)

Chip enable access time

ELQV

a (OE)

Output enable access time

GLQV

DF(CE)

Chip enable high to output in high Z

EHQZ

Read cycle time

AVAV

Output hold from CE#, OE#, addresses

OLZ

GLQX

Output enable to output in low-Z

DF(OE)

GHQZ

Output enable high to output in high Z

PHZ

RP# low to output high-Z

PLQZ

RP# recovery to CE# low

Unit

ns
ns

PHEL

Vcc=2.7-3.6V

150

Max

Min

Typ

90ns

Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at Vcc=3.3V, Ta=25

Symbol

Parameter

Write cycle time

Data hold time

Data set-up time

Address hold time

Address set-up time

AVAV

WHDX

DVWH

WHAX

AVWH

Limits

90ns

Max

Min

Typ

Unit

Write pulse width

Chip enable hold time

Chip enable set-up time

Write pulse width high

RP# high recovery to write enable low

Block Lockhold from valid SRD

Write enable high to F-RY/BY# low

Duration of auto-program operation

Duration of auto-block erase operation

Block Lock set-up to write enable high

WLWH

WHEH

ELWL

WHWL

PHWL

QVPH

WHRL

WHRH1

WHRH2

PHHWH

WHRL

WPH

BLS

BLH

DAP

DAE

OE# hold to WE# Low

GHWL

150

600

ms
ms

Vcc=2.7-3.6V

OE# hold from WE# high

WHGL

OEH

Latency between Read and Write FFH or 71H

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

Erase and Program Performance

Block Erase Time

Main Block Write Time (Page Mode)

Page Write Time

Parameter

sec

Unit

Typ

1.0

Max

1.8

600

Min

Vcc Power Up / Down Timing

Symbol

Unit

Typ

Max

Min

VCS

Parameter

RP# =V

set-up time from Vccmin

During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2

sec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down.

By holding RP# VIL, the contents of memory is protected during Vcc power up/down.
During power up, RP# must be held VIL for min.2

s from the time Vcc reaches Vccmin.

During power down, RP# must be held VIL until Vcc reaches GND.
RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation.

Program Suspend Latency / Erase Suspend Time

Program Suspend Latency

Erase Suspend Time

Parameter

Unit

Typ

Max

Min

Please see page 19.

Please see page 12.

Write Mode (F-CE# control)

AC ELECTRICAL CHARACTERISTICS

(Ta = -40 ~ 85

C, Vcc = 2.7V ~ 3.6V)

Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at Vcc=3.3V, Ta=25

Symbol

Parameter

Write cycle time

Data hold time

Data set-up time

Address hold time

Address set-up time

AVAV

EHDX

DVWH

EHAX

AVWH

Limits

90ns

Max

Min

Typ

Unit

CE# pulse width

Write enable hold time

Write enable set-up time

CE# pulse width high

RP# high recovery to write enable low

Block Lockhold from valid SRD

CE# high to F-RY/BY# low

Duration of auto-program operation

Duration of auto-block erase operation

Block Lock set-up to chip enable high

ELEH

EHWH

WLEL

EHEL

PHWL

QVPH

EHRL

EHRH1

EHRH2

PHHEH

EHRL

CEP

CEPH

BLS

BLH

DAP

DAE

OE# hold to CE# Low

GHEL

150

600

Vcc=2.7-3.6V

OE# hold from CE# high

EHGL

OEH

Latency between Read and Write FFH or 71H

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

3.3V

GND

Vcc POWER UP / DOWN TIMING

RP#

Read /Write Inhibit

VCS

CE#

WE#

Read /Write Inhibit

TEST CONDITIONS
FOR AC CHARACTERISTICS

Input voltage : V

= 0V, V

= 3.0V

Input rise and fall times :

5ns

Reference voltage
at timing measurement : 1.5V

Output load : 1TTL gate +CL(30pF)

or

DUT

3.3k

1N914

1.3V

AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS

OUTPUT VALID

HIGH-Z

DF(OE)

ADDRESSES

CE#

OE#

WE#

DATA

ADDRESS VALID

OLZ

a (CE)

OEH

CLZ

a (AD)

a (OE)

HIGH-Z

RP#

DF(CE)

PHZ

AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION

OUTPUT VALID

HIGH-Z

DF(OE)

ADDRESSES

CE#

OE#

WE#

DATA

ADDRESS VALID

OLZ

a (CE)

CLZ

a (AD)

a (OE)

HIGH-Z

RP#

DF(CE)

PHZ

Valid

FFH or 71H

In the case of use CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)

41H

DIN

WPH

ADDRESS VALID

CE#

OE#

WE#

DATA

DIN

SRD

DIN

OEH

DAP

PROGRAM

READ STATUS

WRITE READ

ARRAY COMMAND

FFH

7FH

01H~7EH

00H

a(CE)

a(OE)

WP1#,
WP2#

BLH

BLS

RP#

BANK ADDRESS VALID

The other bank

address

VALID

DOUT

OEH

GHWL

a(OE)

a(CE)

VALID

A6~A0

A19~A7

DIN

CEPH

CEP

ADDRESS VALID

CE#

OE#

WE#

DATA

DIN

SRD

DIN

OEH

DAP

PROGRAM

READ STATUS

WRITE READ

ARRAY COMMAND

FFH

7FH

01H~7EH

00H

a(CE)

a(OE)

BANK ADDRESS VALID

VALID

DOUT

a(CE)

OEH

GHEL

a(OE)

The other bank

address

A6~A0

A19~A7

RP#

BLH

WP1#,
WP2#

BLS

41H

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)

AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control)

ARRAY READ FROM THE OTHER BANK
WITH BGO

ADDRESS VALID

CE#

OE#

WE#

DATA

7FH

01H~7EH

00H

41H

DIN

DOUT

DIN

SRD

VALID

WPH

a(CE)

a(OE)

OEH

DOUT

PROGRAM DATA TO ONE BANK

Change Bank Address

A6~A0

A19~A7

~ ~
~ ~

~ ~

ARRAY READ FROM THE OTHER BANK
WITH BGO

ADDRESS VALID

CE#

OE#

WE#

DATA

7FH

01H~7EH

00H

41H

DIN

DOUT

DIN

SRD

VALID

CEPH

CEP

a(CE)

a(OE)

OEH

DOUT

PROGRAM DATA TO ONE BANK

Change Bank Address

A6~A0

A19~A7

~ ~

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

FULL STATUS CHECK PROCEDURE

SR.5 = 0 ?

SR.4 = 0 ?

SR.4 =1

and

SR.5 =1

SUCCESSFUL

(BLOCK ERASE, PROGRAM)

YES

STATUS REGISTER

READ

COMMAND SEQUENCE ERROR

BLOCK ERASE ERROR

PROGRAM ERROR

(BLOCK)

WRITE 77H

WRITE D0H

BLOCK ADDRESS

LOCK BIT PROGRAM FLOW CHART

SR.4 = 0 ?

LOCK BIT PROGRAM

SUCCESSFUL

YES

START

LOCK BIT PROGRAM

FAILED

SR.7 = 1 ?

SR.3 = 0 ?

YES

PROGRAM ERROR

(PAGE, LOCK BIT)

PAGE PROGRAM FLOW CHART

START

WRITE 41H

FULL STATUS CHECK

IF DESIRED

PAGE PROGRAM

COMPLETED

YES

n = 0

n = n+1

WRITE

ADDRESS n, DATA n

YES

SR.7 = 1 ?

n = FFH ?

n = 7FH ?

WRITE B0H ?

YES

SUSPEND LOOP

WRITE D0H

YES

STATUS REGISTER

READ

BYTE PROGRAM FLOW CHART

START

WRITE 40H

FULL STATUS CHECK

IF DESIRED

PAGE PROGRAM

COMPLETED

YES

WRITE

ADDRESS , DATA

SR.7 = 1 ?

WRITE B0H ?

YES

SUSPEND LOOP

WRITE D0H

YES

STATUS REGISTER

READ

* Word program is admitted to only BANK(I).

MITSUBISHI LSIs

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29GB/T161BWG

Sep.1999. Rev4.0

SUSPEND / RESUME FLOW CHART

START

WRITE B0H

OPERATION

RESUMED

SR.6 =1?

YES

WRITE FFH

READ ARRAY DATA

DONE

READING ?

YES

WRITE D0H

SUSPEND

RESUME

BLOCK ERASE FLOW CHART

START

WRITE 20H

WRITE D0H

BLOCK ADDRESS

FULL STATUS CHECK

IF DESIRED

YES

SR.7 = 1 ?

WRITE B0H ?

YES

SUSPEND LOOP

WRITE D0H

YES

STATUS REGISTER

READ

BLOCK ERASE

COMPLETED

STATUS REGISTER

READ

SR.7 = 1?

YES

PROGRAM / ERASE

COMPLETED

* The bank address is required when writing this command. Also, there is
no need to suspend the erase or program operation when reading data
from the other bank. Please use BGO function.

SINGLE DATA LOAD TO PAGE BUFFER

START

WRITE 74H

FULL STATUS CHECK

IF DESIRED

PAGE BUFFER TO FLASH

COMPLETED

WRITE

ADDRESS , DATA

WRITE B0H ?

YES

SUSPEND LOOP

WRITE D0H

YES

STATUS REGISTER

READ

WRITE 0EH

WRITE D0H

PAGE ADDRESS

SR.7 = 1 ?

YES

DONE

LOADING?

SINGLE DATA LOAD

TO PAGE BUFFER

COMPLETED

PAGE BUFFER TO FLASH

START

CLEAR PAGE BUFFER

START

WRITE 55H

WRITE D0H

PAGE BUFFER CLEAR

COMPLETED

Part Number M5M29GB161BWG