Document Outline

• CX28365/6/4 x12, x6, x4 T3/E3 Framer and ATM Cell Transmission Convergence Sublayer Processor
• Contents
• Figures
• Tables
• 1.0 Product Description
  • 1.1 Application Overview
    • 1.1.1 Logic Diagram
      • Figure 1-1. CX28365 Logic Diagram, Framer, and Cell Delineator Enabled
      • Figure 1-2. CX28365 Logic Diagram, Cell Delineator Bypassed
  • 1.2 Pin Diagram and Definitions
    • Figure 1-3. CX28365 Pinout Diagram
    • Figure 1-4. CX28366 Pinout Diagram
    • Figure 1-5. CX28364 Pinout Diagram
    • 1.2.1 Pin Definitions
      • Table 1-1. Hardware Signal Definition, Microprocessor Interface (1 of 2)
      • Table 1-2. Hardware Signal Definition, Transmit/Receive Line Interface (1 of 2)
      • Table 1-3. Hardware Signal Definition, Transmit/Receive Systems Interface (1 of 3)
      • Table 1-4. Hardware Signal Definition, ATM UTOPIA Interface (1 of 2)
      • Table 1-5. Hardware Signal Definition, Programmable Input/Output Interface (1 of 2)
      • Table 1-6. Hardware Signal Definition, Power, and Ground (1 of 3)
      • Table 1-7. Hardware Signal Definition, Test, and Control (1 of 2)
• 2.0 Functional Description
  • Figure 2-1. Framer Functional Block Diagram
  • 2.1 T3/E3 Framer
    • 2.1.1 Transmitter Operation
      • 2.1.1.1 Line Signals
        • Figure 2-2. Transmitter Line Outputs
      • 2.1.1.2 System Signals
        • Figure 2-3. Tx System Side External Overhead Insertion (DS3 FEBE-only Example)
        • Figure 2-4. DS3 System Transmit Timing (TxSYNC Indicates Frame Start)
        • Figure 2-5. DS3 System Transmit Timing (TxSync Indicates Overhead Bits)
        • Figure 2-6. DS3 System Transmit Timing (TxSync[i] as Input Indicating Frame Start)
        • Figure 2-7. E3-G.751 System Transmit Timing (TxSYNC Indicates Frame Start)
        • Figure 2-8. E3-G.751 System Transmit Timing (TxSYNC Indicates Overhead Bits)
        • Figure 2-9. E3-G.832 System Transmit Timing (TxSYNC Indicates Frame Start)
        • Figure 2-10. E3-G.832 System Transmit Timing (TxSYNC Indicates Overhead Bits)
      • 2.1.1.3 Transmitter Overhead Bit Generation
        • Table 2-1. Overhead Sourcing Methods
        • Table 2-2. Overhead Choice
      • 2.1.1.4 Alarm Signal Generation
        • Table 2-3. DS3 Mode Alarm Signal Setting
      • 2.1.1.5 Terminal Data Link Transmission
      • 2.1.1.6 FIFO Special Events
      • 2.1.1.7 FEAC Channel Transmission
      • 2.1.1.8 Test Equipment „Error Insertion
        • Table 2-4. Setting the Error Insertion1 Control Register in DS3 Mode
        • Table 2-5. Setting the Error Insertion1 Control Register in E3-G.751 Mode
        • Table 2-6. Setting the Error Insertion1 Control Register in E3-G.832 Mode
        • Figure 2-11. Line Coding Error Insertion
    • 2.1.2 Receiver Operation
      • 2.1.2.1 Line Signals
        • Figure 2-12. Receiver Line Input Timing
      • 2.1.2.2 System Signals
        • Figure 2-13. Receiver System Side Outputs [RxGCKO]
        • Figure 2-14. Receiver System Side Outputs [REXTCKO]
        • Figure 2-15. Receiver System Side Outputs
      • 2.1.2.3 Overhead Bit Recovery
      • 2.1.2.4 Performance Monitoring
      • 2.1.2.5 Terminal Data Link Reception
        • Table 2-7. Status Byte Description
      • 2.1.2.6 FarEnd Alarm and Control Channel Reception
  • 2.2 ATM Cell Processor
    • 2.2.1 ATM Cell Transmitter
      • 2.2.1.1 HEC Generation
    • 2.2.2 ATM Cell Receiver
      • 2.2.2.1 HEC Based Cell Delineation
        • Figure 2-16. Cell Delineation Process
        • Figure 2-17. Header Error Check Process
    • 2.2.3 PLCP Cell Generation for Transmit
      • Table 2-8. FEBE Controls
      • Table 2-9. C1 Octet
    • 2.2.4 PLCP Cell Validation for Receive
      • 2.2.4.1 PLCP Status
    • 2.2.5 PLCP Transmit/Receive Synchronization
    • 2.2.6 Cell Screening
      • Table 2-10. Cell Screening„Matching
      • Table 2-11. Cell Screening„Accept/Reject Cell
    • 2.2.7 Cell Scrambler
      • 2.2.7.1 SSS Scrambling
  • 2.3 UTOPIA Interface
    • 2.3.1 UTOPIA Transmit and Receive FIFOs
    • 2.3.2 UTOPIA 8-bit and 16-bit Bus Widths
      • Table 2-12. Cell Format for 8-bit Mode
      • Table 2-13. Cell Format for 16-bit Mode
    • 2.3.3 UTOPIA Parity
    • 2.3.4 UTOPIA Multi-PHY Operation
    • 2.3.5 UTOPIA Addressing
    • 2.3.6 Handshaking
  • 2.4 Interfacing
    • 2.4.1 Microprocessor Interface
      • 2.4.1.1 Resets
        • Table 2-14. Reset Control
    • 2.4.2 Input/Output Ports
      • Figure 2-18. Input/Output Ports Application Example (LIU Control)
    • 2.4.3 Counters
    • 2.4.4 One-Second Latching
    • 2.4.5 External Framer Interrupts and Chip Selects
    • 2.4.6 Interrupts
      • 2.4.6.1 Interrupt Routing
        • Figure 2-19. Input/Output Ports Application Example (Framer and LIU Control)
  • 2.5 Loopback
    • 2.5.1 Cell Delineator Source Loopback
      • Figure 2-20. Source Loopback Diagram
    • 2.5.2 Far-End Line Loopback
      • Figure 2-21. Far-End Line Loopback Diagram
    • 2.5.3 Framer Loopbacks
      • Figure 2-22. Loopback Types
      • 2.5.3.1 Shallow Line Loopback
      • 2.5.3.2 Remote Line Loopback
      • 2.5.3.3 Payload Loopback
  • 2.6 Joint Test Access Group (JTAG) Interface
    • Figure 2-23. TAP Diagram
    • 2.6.1 Instructions
      • Table 2-15. JTAG Instruction Codes
    • 2.6.2 Device Identification Register
      • Table 2-16. CX28394 Device Identification JTAG Register
• 3.0 Registers
  • 3.1 Register Map
    • Table 3-1. Cell Delineator Register Map
    • Table 3-2. Cell Delineator Control and Status Registers (1 of 3)
    • Table 3-3. PLCP Register Map
    • Table 3-4. PLCP Registers
    • Table 3-5. Framer Register Map
    • Table 3-6. Framer Registers
    • Table 3-7. Common Registers (1 of 2)
    • Table 3-8. External Chip Select Address Map
  • 3.2 Cell Delineator Registers
    • 3.2.1 Mode Control Registers
    • 3.2.2 Cell Transmit Registers
    • 3.2.3 Cell Receive Registers
      • Table 3-9. Control Bit Function
    • 3.2.4 UTOPIA Registers
    • 3.2.5 Status and Interrupt Registers
    • 3.2.6 Counters
  • 3.3 PLCP Registers
  • 3.4 Framer Registers
    • 3.4.1 Feature Control Registers
    • 3.4.2 Transmitter Registers
      • Table 3-10. DS3-C-Bit Parity/E3-G.751 Mode Field Interpretation
      • Table 3-11. E3-G.832 Mode Field Interpretation 
    • 3.4.3 Receiver Registers
    • 3.4.4 Data Link Registers
    • 3.4.5 Error Insertion Control Registers
    • 3.4.6 Framer Channel Status Registers
    • 3.4.7 Dual-Edge Interrupt Status Registers
    • 3.4.8 E3-832 MA Fields Registers
    • 3.4.9 Counters
  • 3.5 Common Global Registers (0xE00„0xE7F)
• 4.0 Specifications
  • 4.1 Absolute Maximum Ratings
    • Table 4-1. Absolute Maximum Ratings
  • 4.2 Recommended Operating Conditions
    • Table 4-2. Recommended Operating Conditions (Table 4-2 in the Data Sheet)
  • 4.3 DC Characteristics
    • Table 4-3. DC Characteristics
  • 4.4 AC Characteristics
    • 4.4.1 Clock And Signal Timing
      • Figure 4-1. Input Waveform
      • Figure 4-2. Output Waveform
      • Figure 4-3. Input Hysteresis (Schmitt Trigger Input)
      • 4.4.1.1 Input Clock Timing
        • Figure 4-4. Input Clock Timing
        • Table 4-4. Input Clock Timing
        • Figure 4-5. Line Side Receiver Input Data Setup/Hold Timing
        • Figure 4-6. Line Side Transmitter Output Data Timing
        • Figure 4-7. System-Side Transmitter Interface Timing
        • Figure 4-8. System-Side Receiver Interface Timing
        • Table 4-5. Output Signal Timing
        • Table 4-6. Input Signal Timing
    • 4.4.2 Microprocessor Timing
      • Figure 4-9. Microprocessor„Read Timing
      • Table 4-7. Microprocessor„Read Timing
      • Figure 4-10. Microprocessor„Write Timing
      • Table 4-8. Microprocessor„Write Timing
      • 4.4.2.1 Additional Restrictions
    • 4.4.3 UTOPIA Interface Timing
      • Figure 4-11. UTOPIA Transmit Timing
      • Table 4-9. UTOPIA Transmit Timing
      • Figure 4-12. UTOPIA Receive Timing
      • Table 4-10. UTOPIA Receive Timing
    • 4.4.4 One-Second Interface Timing
      • Figure 4-13. One-Second Timing
      • Table 4-11. One-Second Timing(1)
    • 4.4.5 MReset* Timing
      • Table 4-12. Reset Timing
      • Figure 4-14. MReset Timing
    • 4.4.6 JTAG Interface Timing
      • Figure 4-15. JTAG Timing
      • Table 4-13. JTAG Timing
• 5.0 Package Specifications
  • Figure 5-1. Package Drawing
• Appendix A: Device Initialization
• Appendix B: Frame Structure Summary
  • Table B-1. Overhead Bits in DS3 Mode
  • Table B-2. Overhead Bits in E3-G751 Mode
  • Table B-3. Overhead Bytes in E3-G832
• Appendix C: B3ZS/HDB3 Encoding
• Appendix D: Acronyms
• Sales Offices