1
P/N:PM0652
REV. 1.5, MAR. 11, 2003
FEATURES
· Bit organization
- 4M x 16 (word mode only)
- 256 words/page
- Total 16K pages
· Sequential access at 200ns cycle time in a page
· Asynchronous chip enable input (ALEH, ALEL)
· Access time
- Read latency time: 950ns
- Read cycle time: 200ns
- RD access time: 150ns
· Current
- Operating:25mA(max.)
- Address input:2mA(max.)
- Standby:20uA(max.)
· Supply voltage
- 3.0V~3.6V
· Package
- 32 pin TSOP
ORDER INFORMATION
Part No.
Read Cycle Time
Package
MX23L6412TC-20
200ns
32 pin TSOP
GENERAL DESCRIPTION
The product is a 64M bits (4M x 16) mask ROM
composed of 16K pages, and each consists of 256 words
memory cell array. This mask ROM has a 16 bit address
input / data output bus (AD0~AD15), two address latch
enable pins (high : ALEH, low : ALEL), a read strobe
(RD).
There are 3 modes, Stand-by mode, Active mode, and
Address input mode. Stand-by mode is a non-operating
state, and has the smallest current dissipation. Active
mode is an operating state, and data output is possible.
Address input mode is a state of address input.
Address input is through AD bus when ALEL is high.
The high and low 16 bit addresses are latched at
ALEH'sand ALEL falling edges. As for high 16 bit ad-
dress, A0~A6 are through 7 bit address register, A7~A15
are not used internally. As for low 16 bit address, A1~A8
are through 8 bit address counter, A9~A15 are through 7
bit address register, and A0 are not used internally. High
address input must be done before low address input,
and both address inputs are needed for page change or
address change in a same page. After address inputs,
CE goes high at ALEH falling edge and RD doesn't toggle,
the ROM is in stand-by mode.
After ROM turned into Active mode from Address input
mode, it takes tL time to read. In a page, sequential
read access is possible at tCYC cycle time. Sequential
read operation (increment of internal address counter) is
done at every falling edge of RD. At the end of a page,
internal address counter raps around to the beginning of
the page.
MX23L6412
SEQUENTIAL 64M-BIT MASK ROM
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P/N:PM0652
REV. 1.5, MAR. 11, 2003
MX23L6412
PIN CONFIGURATION
PIN DESCRIPTION
Symbol
Pin Function
AD0~AD15
Address Input / Data Output
ALEH
Address Latch Enable High
ALEL
Address Latch Enable Low
CE
Chip Enable Input
RD
Read Strobe Input
VCC
Power Supply Pin
VSS
Ground Pin
NC
No Connection
BLOCK DIAGRAM
RD
ALEH
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ALEL
CE
Enable
Enable
Column Decoder
Address
Register
Clock
Input Buff
er
Ro
w Decoder
Output Buff
er
Latch x 16
Memory Cell Array
256 words/ Page
CE
Reg.
Address
Register
Address
Presettable
Counter
32 TSOP
NC
CE
VSS
AD12
AD13
AD14
AD15
NC
NC
AD0
AD1
AD2
AD3
VCC
ALEL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
RD
VCC
AD11
AD10
AD9
AD8
NC
NC
AD7
AD6
AD5
AD4
VSS
ALEH
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX23L6412
TRUTH TABLE
Mode
Operation
CE
ALEH
ALEL
RD
AD Bus
Address Input
High address input
L
H
H
X
Address input
Address Input
Low address input
X
L
H
X
Address input
Active
Internally active
X
L
L
H
Floating
Active
Data read
X
L
L
L
Data output
Stand-by
Stand-by *
X
H-->L
L
X
Floating
Note: Please see "standby mode" timing diagram.
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P/N:PM0652
REV. 1.5, MAR. 11, 2003
MX23L6412
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
Voltage on any Pin Relative to VSS
VIN
-0.5V to 4.6V
Ambient Operating Temperature
Topr
0
°
C to 70
°
C
Storage Temperature
Tstg
-55
°
C to 125
°
C
DC CHARACTERISTICS (Ta = 0
°
C~70
°
C, VCC = 3.3V
±
10%)
Item
Symbol
MIN.
MAX.
Conditions
Output High Voltage
VOH
2.0V
-
IOH = -0.4mA
Output Low Voltage
VOL
-
0.4V
IOL = 2mA
Input High Voltage
VIH
2.0V
VCC+0.5V
Input Low Voltage
VIL
-0.5V
0.8V
Input Leakage Current
ILI
-10uA
10uA
VIN = 0V to 3.6V
Output Leakage Current
ILO
-10uA
10uA
VOUT = 0V to 3.6V
Operating Current
ICC1
-
25mA
Cycle = 200ns, VIN = VIH or VIL, active mode
Address Input Current
ICC2
-
2mA
Cycle = 100ns, VIN = VIH or VIL, address
input mode
Standby Current (CMOS)
ISTB
-
20uA
Cycle = 200ns, VIN = VCC
±±
±±
±
0.3V or
0V
±±
±±
±
0.3V,stand-by mode
Input Capacitance
CIN
-
12pF
Ta = 25
°
C, f = 5MHz, VIN = 0V
Output Capacitance
COUT
-
12pF
Ta = 25
°
C, f = 5MHz, VOUT = 0V
AC CHARACTERISTICS (Ta = 0° C~70° C, VCC = 3.3V
±
10%)
Item
Symbol
MIN.
MAX.
Conditions
ALEL Setup Time
tALES
70ns
ALE Delay Time
tALED
70ns
Address Setup Time
tAS
30ns
Address Hold Time
tAH
0
Read Latency Time
tL
950ns
Read Cycle Time
tCYC
200ns
CE Setup Time
tCES
50ns
CE Hold Time
tCEH
0ns
RD Access Time
tRD
150ns
RD High Time
tRDH
50ns
Output Hold Time
tOH
0
Output Float Time
tDF
40ns
Release Time
tR
0
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