MAX1338 DS

General Description

The MAX1338 14-bit, analog-to-digital converter (ADC)
offers four simultaneously sampled, fully differential input
channels, with independent track-and-hold (T/H) circuitry
for each channel. The input channels are individually
software programmable for input ranges of ±10V, ±5V,
±2.5V, and ±1.25V. The input channels feature fault tol-
erance to ±17V. The internal T/H circuits have a 16ns
aperture delay and 100ps aperture-delay matching.

A 14-bit parallel bus provides the conversion result with
a maximum per-channel output rate of 150ksps
(600ksps for all four channels). The MAX1338 has an
on-board oscillator and 2.5V internal reference. An
external clock and/or reference can also be used.

The MAX1338 operates from a +5V supply for analog
inputs and digital core. The device operates from a +2.7V
to +5.25V supply for the digital I/O lines. The MAX1338
features two power-saving modes: standby mode and
shutdown mode. Standby mode allows rapid wake-up
and reduces quiescent current to 4mA (typ), and shut-
down mode reduces sleep current to less than 10µA (typ).

The MAX1338 is available in an 8mm x 8mm x 0.8mm,
56-pin, thin QFN package. The device operates over
the extended -40°C to +85°C temperature range.

Applications

Multiple-Channel Data Recorders

Vibration Analysis

Motor Control: 3-Phase Voltage, Current, and
Power Measurement

Optical Communication Equipment

Features

150ksps Sample Rate per Channel

All Four Input Channels Simultaneously Sampled

16ns Aperture Delay
100ps Aperture-Delay Matching

Channel-Independent Software-Selectable Input

Range: ±10V, ±5V, ±2.5V, ±1.25V

±17V Fault-Tolerant Inputs

Dynamic Performance at 10kHz Input

SNR: 77dB
SINAD: 76dB
SFDR: 98dBc
THD: -83dBc

DC Performance

INL: ±2 LSB
DNL: ±1 LSB
Offset Error: ±4 LSB
Gain Error: ±0.1% FSR

14-Bit Parallel Interface

Internal Clock and Reference Voltage

+5V Analog and Digital Supplies

+2.7V to +5.25V Digital I/O Supply

56-Pin Thin QFN Package (8mm x 8mm x 0.8mm)

MAX1338

14-Bit, 4-Channel, Software-Programmable,

Multiranging, Simultaneous-Sampling ADC

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-3151; Rev 0; 4/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

PART

TEMP RANGE

PIN-PACKAGE

MAX1338ETN

-40

C to +85

56 Thin QFN-EP*

*EP = Exposed pad.

Pin Configuration appears at end of data sheet.

MAX1338

14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC

_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

to AGND .........................................................-0.3V to +6V

to DGND.........................................................-0.3V to +6V

DRV

to DRGND ....................................................-0.3V to +6V

to DV

.......................................................-0.3V to +0.3V

DGND to DRGND ..................................................-0.3V to +0.3V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to DRGND ..................................................-0.3V to +0.3V
AIN0+, AIN0-, AIN1+, AIN1-, AIN2+, AIN2-, AIN3+,

AIN3- to AGND .....................................................-17V to +17V

D0D13 to DRGND................................-0.3V to (DRV

+ 0.3V)

REFADC, REFP1, REFP2, REFN1, REFN2, COM1, COM2 to

AGND....................................................-0.3V to (AV

+ 0.3V)

INTCLK/EXTCLK to AGND.......................-0.3V to (AV

+ 0.3V)

CS, RD, WR, CONVST, to DRGND........-0.3V to (DRV

+ 0.3V)

SHDN, STANDBY, CLK, EOC,

EOLC to DRGND ................................-0.3V to (DRV

+ 0.3V)

Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T

= +70°C)

56-Pin Thin QFN (derate 31.3mW /°C above +70°C)....2500mW

Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Junction to Ambient Thermal Resistance

..................32°C/W

Junction to Case Thermal Resistance

.........................2°C/W

ELECTRICAL CHARACTERISTICS

(AV

= DV

= +5.0V, DRV

= +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f

CLK

= 5MHz, input range =

±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND,
0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at T

= +25°C. T

= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

INL

(Note 1)

LSB

Differential Nonlinearity

DNL

No missing codes (Note 1)

0.25

LSB

Offset Error

(Note 1)

LSB

Offset-Error Temperature
Coefficient

ppm/°C

Offset-Error Matching

LSB

Gain Error

Offset nulled (Notes 1, 2)

0.1

0.35

%FSR

Channel Gain-Error Matching

Offset nulled

LSB

Gain-Error Temperature
Coefficient

Offset nulled

ppm/

DYNAMIC PERFORMANCE

(at f

= 10kHz, A

= -0.2dBFS)

Sampling Rate Per Channel

Simultaneous on all channels

150

ksps

Signal-to-Noise Ratio

SNR

(Note 1)

Signal-to-Noise Plus Distortion

SINAD

(Note 1)

Total Harmonic Distortion

THD

(Note 1)

-83

-80

dBc

Spurious-Free Dynamic Range

SFDR

Range 0 (Note 1)

dBc

Channel-to-Channel Isolation

(Note 1)

ANALOG INPUTS

(AIN_)

Range set bits = (0,0)

-10

+10

Range set bits = (0,1)

-5

Range set bits = (1,0)

-2.5

+2.5

Input Differential Voltage Range

Range set bits = (1,1)

-1.25

+1.25

MAX1338

14-Bit, 4-Channel, Software-Programmable,

Multiranging, Simultaneous-Sampling ADC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +5.0V, DRV

= +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f

CLK

= 5MHz, input range =

= +25°C. T

= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Range set bits = (0,0)

-5

Range set bits = (0,1)

-2.5

+2.5

Range set bits = (1,0)

-1.25

+1.25

Input Common-Mode Range

Range set bits = (1,1)

-0.625

+0.625

Input Resistance

All settings

6.25

Input Capacitance

Small-Signal Bandwidth

SSBW

(Note 1)

MHz

Full-Power Bandwidth

FPBW

(Note 1)

kHz

INTERNAL REFERENCE

(REFADC)

Output Voltage

2.475

2.5

2.525

Differential Reference Voltage

REFP

REFN

2.5

Output-Voltage Temperature
Coefficient

ppm/

Load Regulation

V/mA

EXTERNAL REFERENCE

REFADC Voltage Input Range

2.0

2.5

3.0

REFADC Input Current

(Note 3)

-250

+250

µA

REFADC Input Resistance

REF

REFADC Input Capacitance

TRACK/HOLD (T/H)

Aperture Delay

(Note 1)

Aperture-Delay Matching

100

Aperture Jitter

(Note 1)

RMS

CLOCK-SELECT INPUT

(INTCLK/

EXTCLK

)

Input-Voltage High

0.7 x

Input-Voltage Low

0.3 x

DIGITAL INTERFACE AND CONTROL INPUTS

(

, CONVST, SHDN, CLK, STANDBY)

Input-Voltage High

0.7 x

DRV

Input-Voltage Low

0.3 x

DRV

Input Hysteresis

Input Capacitance

MAX1338

14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +5.0V, DRV

= +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f

CLK

= 5MHz, input range =

= +25°C. T

= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Current

= 0 or DRV

±1

µA

DIGITAL INTERFACE AND CONTROL OUTPUTS

(

EOC

EOLC

)

Output-Voltage High

Sourcing 0.8mA

DRV

- 0.6

Output-Voltage Low

Sinking 1.6mA

0.4

PARALLEL DIGITAL I/O (D0D7)

Output-Voltage High

Sourcing 0.8mA

DRV

0.6

Output-Voltage Low

Sinking 1.6mA

0.4

Leakage Current

µA

Tristate Output Capacitance

RD = 1 or CS = 1

Input-Voltage High

0.7 x

DRV

Input-Voltage Low

0.3 x

DRV

Input Hysteresis

Input Capacitance

Input Current

= 0 or DRV

±1

µA

PARALLEL DIGITAL OUTPUTS (D8D13)

Output-Voltage High

Sourcing 0.8mA

DRV

0.6

Output-Voltage Low

Sinking 1.6mA

0.4

Leakage Current

µA

Tristate Output Capacitance

POWER SUPPLIES

Analog Supply Voltage

4.75

5.25

Digital Supply Voltage

4.75

5.25

Parallel Digital I/O Supply Voltage

DRV

2.70

5.25

SHDN = 1

0.005

0.1

Analog Supply Current

STANDBY = 1, SHDN = 0

4.2

SHDN = 1

0.001

0.05

Digital Supply Current

STANDBY = 1, SHDN = 0

0.001

0.05

SHDN = 1

0.05

Digital Driver Supply Current

DRI

STANDBY = 1, SHDN = 0

0.05

Analog Power-Supply Rejection

4.75V to 5.25V (Note 1)

MAX1338

14-Bit, 4-Channel, Software-Programmable,

Multiranging, Simultaneous-Sampling ADC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= +5.0V, DRV

= +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f

CLK

= 5MHz, input range =

= +25°C. T

= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS

(Figures 4, 5, and 6)

Internal clock

2.9

3.2

3.5

µs

Time to First Conversion Result

EOC1

External clock

CLK

Cycles

Internal clock

600

Time to Subsequent Conversions

External clock

CLK

Cycles

CONVST Pulse-Width Low

CONVST

0.1

µs

CS Pulse Width

RD Pulse-Width Low

RDL

RD Pulse-Width High

RDH

WR Pulse-Width Low

WRL

CS to WR Setup Time

CTW

WR to CS Hold Time

WTC

CS to RD Setup Time

CTR

RD to CS Hold Time

RTC

Data Access Time
(RD Low to Valid Data)

ACC

Figure 1

Bus Relinquish Time
(RD High to D_ High-Z)

REQ

Figure 1

CLK Rise to End-of-Conversion
(EOC) Rise/Fall Delay

EOCD

CLK Rise to End-of-Last-
Conversion (EOLC) Fall Delay

EOLCD

CONVST Rise to EOLC Fall Delay

CVEOLCD

Internal clock

180

200

EOC Pulse-Width Low

EOC

External clock

CLK

Cycle

Wake-Up Time From Standby

µs

Wake-Up Time From Shutdown

All bypass capacitors discharged

Part Number MAX1338