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This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000041-00, First Edition (July 1998)
This document describes revision A of LSI Logic Corporation's L64105 MPEG-2
Audio/Video Decoder and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);
+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)
and ask for Department JDS; or visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
In particular, supply of the LSI Logic IC L64105 does not convey a license or
imply a right under certain patents and/or other industrial or intellectual property
rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use
electronic product. The purchaser is hereby notified that Philips, CCETT and IRT
are of the opinion that a generally available patent license for such use is
required from them. No warranty or indemnity of any sort is provided by LSI Logic
regarding patent infringement.
Copyright © 1997, 1998 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and G10 are registered trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.
Contents
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Contents
Preface
Chapter 1
Introduction
1.1
An L64105 Application
1-1
1.2
L64105 Overview
1-2
1.2.1
Memory Utilization
1-5
1.2.2
Error Concealment
1-5
1.3
Features
1-6
Chapter 2
I/O Signal Descriptions
2.1
Signals Organization
2-1
2.2
Host Interface
2-3
2.3
Channel Interface
2-5
2.4
Memory Interface
2-7
2.5
Video Interface
2-8
2.6
Audio Interface
2-9
2.7
Miscellaneous and Test Interfaces
2-11
Chapter 3
Register Summary
3.1
Summary by Register
3-1
3.2
Alphabetical Listing
3-30
Chapter 4
Register Descriptions
4.1
Host Interface Registers
4-2
4.2
Video Decoder Registers
4-17
4.3
Memory Interface Registers
4-38
4.4
Microcontroller Registers
4-48
iv
Contents
4.5
Video Interface Registers
4-58
4.6
Audio Decoder Registers
4-72
4.7
RAM Test Registers
4-91
Chapter 5
Host Interface
5.1
Overview
5-1
5.2
Interface Signals
5-2
5.3
Register Access and Functions
5-5
5.3.1
General Functions
5-5
5.3.2
SCR Registers
5-6
5.3.3
Interrupt Registers
5-9
5.4
SDRAM Access
5-10
5.4.1
Host Reads/Writes
5-10
5.4.2
Host DMA SDRAM Transfers
5-14
5.4.3
SDRAM Block Move
5-18
Chapter 6
Channel Interface
6.1
Overview
6-1
6.2
Interface Signals Operation
6-3
6.2.1
Asynchronous Mode
6-4
6.2.2
Synchronous VALIDn Inputs
6-5
6.2.3
Synchronous A/VREQn Outputs
6-7
6.2.4
Channel Bypass Mode
6-8
6.2.5
Channel Pause
6-8
6.3
Preparser
6-9
6.3.1
Host Selection of Streams and Headers
6-9
6.3.2
Elementary Streams
6-12
6.3.3
PES Packet Structure
6-14
6.3.4
Preparsing an MPEG-1 System Stream
6-16
6.3.5
Preparsing a Program Stream
6-18
6.3.6
Error Handling in Program Streams
6-21
6.3.7
Preparsing A/V PES Packets from a
Transport Stream
6-24
6.3.8
Error Handling in A/V PES Mode
6-25
6.4
Channel Buffer Controller
6-27
6.4.1
Buffer Reset
6-28
Contents
v
6.4.2
Detecting Potential Underflow Conditions
in the Video Channel
6-29
6.5
Summary
6-30
Chapter 7
Memory Interface
7.1
Overview
7-1
7.2
SDRAM Configurations
7-2
7.3
SDRAM Timing and Modes
7-3
7.4
SDRAM Refresh and Arbitration
7-5
7.5
Memory Channel Buffer Allocation
7-6
7.6
Memory Frame Store Allocation
7-9
7.6.1
Luma Store
7-9
7.6.2
Chroma Store
7-9
7.6.3
Normal Mode
7-10
7.6.4
Reduced Memory Mode (RMM)
7-11
7.7
Summary
7-12
Chapter 8
Video Decoder Module
8.1
Overview
8-1
8.2
Postparser Operation
8-4
8.2.1
Sequence Header
8-4
8.2.2
Sequence Extension
8-6
8.2.3
Sequence Display Extension
8-7
8.2.4
Group of Pictures Header
8-8
8.2.5
Picture Header
8-9
8.2.6
Picture Coding Extension
8-11
8.2.7
Quant Matrix Extension
8-13
8.2.8
Host Access of Q Table Entries
8-14
8.2.9
Picture Display Extension
8-15
8.2.10
Copyright Extension
8-17
8.2.11
User Data
8-18
8.2.12
Picture Data
8-18
8.2.13
Unsupported Syntax
8-18
8.2.14
Auxiliary Data FIFO Operation
8-19
8.2.15
User Data FIFO Operation
8-21
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