LTC3407-2

sn34072 34072fs

APPLICATIO S

FEATURES

TYPICAL APPLICATIO

DESCRIPTIO

PDAs/Palmtop PCs

Digital Cameras

Cellular Phones

Portable Media Players

PC Cards

Wireless and DSL Modems

High Efficiency: Up to 95%

Very Low Quiescent Current: Only 40µA

2.25MHz Constant Frequency Operation

High Switch Current: 1.2A on Each Channel

No Schottky Diodes Required

Low R

DS(ON)

Internal Switches: 0.35

Current Mode Operation for Excellent Line
and Load Transient Response

Short-Circuit Protected

Low Dropout Operation: 100% Duty Cycle

Ultralow Shutdown Current: I

< 1µA

Output Voltages from 5V down to 0.6V

Power-On Reset Output

Externally Synchronizable Oscillator

Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages

Dual Synchronous, 800mA,

2.25MHz Step-Down

DC/DC Regulator

The LTC

3407-2 is a dual, constant frequency, synchro-

nous step down DC/DC converter. Intended for low power
applications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile 1.2mm. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35, 1.2A power
switches provide high efficiency without the need for
external Schottky diodes.

A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode

operation provides high efficiency at light loads,

while Pulse Skip Mode provides low noise ripple at light
loads.

To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40µA. In shutdown, the device draws <1µA.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

LTC3407-2 Efficiency Curve

Figure 1. 2.5V/1.8V at 800mA Step-Down Regulators

RUN2

= 2.5V*

TO 5.5V

OUT2

= 2.5V

AT 800mA

OUT1

= 1.8V

AT 800mA

RUN1

POR

SW1

FB1

GND

FB2

SW2

MODE/SYNC

LTC3407-2

C1
10µF

R5
100k

RESET

C4, 22pF

C5, 22pF

2.2µH

887k

604k

R1
301k

280k

10µF

C2
10µF

3407 TA01

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN2R2M33

OUT

CONNECTED TO V

FOR V

2.8V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 TA02

= 3.3V

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

2.5V

1.8V

LTC3407-2

sn34072 34072fs

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

DD PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

FB2

RUN2

POR

SW2

MODE/
SYNC

FB1

RUN1

SW1

GND

Voltages ................................................. 0.3V to 6V

FB1

, V

FB2

, RUN1, RUN2

Voltages ..................................... 0.3V to V

+ 0.3V

MODE/SYNC Voltage ...................... 0.3V to V

+ 0.3V

SW1, SW2 Voltage ......................... 0.3V to V

+ 0.3V

POR Voltage ................................................ 0.3V to 6V

ABSOLUTE AXI U

RATI GS

(Note 1)

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25°C. V

= 3.6V, unless otherwise specified. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Voltage Range

2.5

5.5

Feedback Pin Input Current

Feedback Voltage (Note 3)

0°C T

85°C

0.588

0.6

0.612

40°C T

85°C

0.585

0.6

0.612

LINE REG

Reference Voltage Line Regulation

= 2.5V to 5.5V (Note 3)

0.3

0.5

%/V

LOAD REG

Output Voltage Load Regulation

(Note 3)

0.5

Input DC Supply Current

Active Mode

FB1

= V

FB2

= 0.5V

700

950

µA

Sleep Mode

FB1

= V

FB2

= 0.63V, MODE/SYNC = 3.6V

µA

Shutdown

RUN = 0V, V

= 5.5V, MODE/SYNC = 0V

0.1

µA

OSC

Oscillator Frequency

FBX

= 0.6V

1.8

2.25

2.7

MHz

SYNC

Synchronization Frequency

2.25

MHz

LIM

Peak Switch Current Limit

= 3V, V

FBX

= 0.5V, Duty Cycle <35%

0.95

1.2

1.6

DS(ON)

Top Switch On-Resistance

(Note 6)

0.35

0.45

Bottom Switch On-Resistance

(Note 6)

0.30

0.45

SW(LKG)

Switch Leakage Current

= 5V, V

RUN

= 0V, V

FBX

= 0V

0.01

µA

Ambient Operating Temperature

Range (Note 2) ................................... 40°C to 85°C

Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range ................. 65°C to 125°C
Lead Temperature (Soldering, 10 sec)

LTC3407-2EMSE only ...................................... 300°C

Reflow Peak Body Temperature ............................ 260°C

ORDER PART

NUMBER

DD PART MARKING

JMAX

= 125°C,

= 45°C/W,

= 10°C/W

LBFB

LTC3407EDD-2

PACKAGE/ORDER I FOR ATIO

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER PART

NUMBER

MSE PART MARKING

JMAX

= 125°C,

= 45°C/W,

= 10°C/W

LTBDZ

LTC3407EMSE-2

TOP VIEW

1
2
3
4
5

FB1

RUN1

SW1

GND

10
9
8
7
6

FB2

RUN2
POR
SW2
MODE/
SYNC

MSE PACKAGE

10-LEAD PLASTIC MSOP

MSE PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

LTC3407-2

sn34072 34072fs

TYPICAL PERFOR A CE CHARACTERISTICS

Load Step

Burst Mode Operation

Pulse Skipping Mode

Efficiency vs Input Voltage

Oscillator Frequency vs Supply
Voltage

Oscillator Frequency vs
Temperature

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3407-2E is guaranteed to meet specified performance
from 0°C to 70°C. Specifications over the 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3407-2 is tested in a proprietary test mode that connects

to the output of the error amplifier.

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Note 5: T

is calculated from the ambient T

and power dissipation P

according to the following formula: T

= T

+ (P

Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25°C. V

= 3.6V, unless otherwise specified. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

POR

Power-On Reset Threshold

FBX

Ramping Up, MODE/SYNC = 0V

8.5

FBX

Ramping Down, MODE/SYNC = 0V

8.5

Power-On Reset On-Resistance

100

200

Power-On Reset Delay

262,144

Cycles

RUN

RUN Threshold

0.3

1.5

RUN

RUN Leakage Current

0.01

µA

2.5

2.4

2.3

2.2

2.1

2.0

FREQUENCY (MHz)

FREQUENCY DEVIATION (%)

SUPPLY VOLTAGE (V)

3407 G06

INPUT VOLTAGE (V)

3407 G04

3407 G01

3407 G02

3407 G03

TEMPERATURE (°C)

3407 G05

100

125

100

EFFICIENCY (%)

= 3.6V

OUT

= 1.8V

LOAD

= 100mA

CIRCUIT OF FIGURE 1

= 3.6V

OUT

= 1.8V

LOAD

= 20mA

CIRCUIT OF FIGURE 1

= 3.6V

OUT

= 1.8V

LOAD

= 80mA TO 800mA

CIRCUIT OF FIGURE 1

OUT

= 1.8V

Burst Mode OPERATION
CIRCUIT OF FIGURE 1

800mA

10mA

100mA

1mA

5V/DIV

OUT

100mV/DIV

200mA/DIV

5V/DIV

OUT

10mV/DIV

200mA/DIV

OUT

200mV/DIV

500mA/DIV

LOAD

500mA/DIV

2µs/DIV

1µs/DIV

20µs/DIV

= 3.6V

= 25°C unless other wise specified.

LTC3407-2

sn34072 34072fs

(V)

OUT

ERROR (%)

0.5

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

3407 G15

OUT

= 1.8V

OUT

= 200mA

= 25°C

(V)

500

450

400

350

300

250

200

3407 G08

DS(ON)

)

MAIN
SWITCH

SYNCHRONOUS

SWITCH

0.615

0.610

0.605

0.600

0.595

0.590

0.585

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

550

500

450

400

350

300

250

200

150

100

3407 G09

100

150

125

TEMPERATURE (°C)

3407 G07

100

125

DS(ON)

)

MAIN SWITCH
SYNCHRONOUS SWITCH

= 3.6V

= 4.2V

= 2.7V

= 25°C

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 G10

3.6V

2.7V

4.2V

OUT

= 2.5V

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 G13

2.7V

4.2V

OUT

= 1.2V

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 G14

2.7V

4.2V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 G11

= 3.6V, V

OUT

= 1.8V

NO LOAD ON OTHER CHANNEL

LOAD CURRENT (mA)

OUT

ERROR (%)

100

1000

3407 G12

= 3.6V, V

OUT

= 1.8V

NO LOAD ON OTHER CHANNEL

Burst Mode OPERATION

PULSE SKIP MODE

OUT

= 1.5V

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1

3.6V

Efficiency vs Load Current

Load Regulation

Efficiency vs Load Current

Line Regulation

TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage vs
Temperature

DS(ON)

vs Input Voltage

DS(ON)

vs Temperature

LTC3407-2

sn34072 34072fs

FB1

(Pin 1): Output Feedback. Receives the feedback

voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.

RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to V

enables regulator 1, while forcing it to GND causes regu-
lator 1 to shut down.

(Pin 3): Main Power Supply. Must be closely decoupled

to GND.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from V

to GND.

GND (Pin 5): Main Ground. Connect to the () terminal of
C

OUT

, and () terminal of C

MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation
of the device. When tied to V

or GND, Burst Mode

operation or pulse skipping mode is selected, respec-
tively. Do not float this pin. The oscillation frequency can

PI FU CTIO S

be syncronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.

SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from V

to GND.

POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage is not
within ±8.5% of regulation and goes high after 117ms
when both channels are within regulation.

RUN2 (Pin 9): Output Feedback. Forcing this pin to V

enables regulator 2, while forcing it to GND causes regu-
lator 2 to shut down.

FB2

(Pin 10): Output Feedback. Receives the feedback

voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.

Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the () terminal of C

OUT

, and () terminal of C

. Must be

connected to electrical ground on PCB.

LTC3407-2

sn34072 34072fs

The LTC3407-2 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and high efficiency.

The output voltage is set by an external divider returned to
the V

pins. An error amplfier compares the divided

output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
will go high after 262,144 clock cycles (about 117ms) of
achieving regulation.

OPERATIO

BLOCK DIAGRA

UVDET

OVDET

0.6V

0.65V

0.55V

0.35V

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

LATCH

BURST

COMP

RCMP

ANTI

SHOOT-

THRU

BURST

CLAMP

SLOPE

COMP

SLEEP

POR

COUNTER

0.6V REF

OSC

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

PGOOD1

PGOOD2

SHUTDOWN

REGULATOR 1

SW1

GND

POR

GND

SW2

MODE/SYNC

FB1

RUN1

RUN2

FB2

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V

voltage is below the the reference voltage.

The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the internally
compensated I

voltage, which is the output of the error

amplifier.This amplifier compares the V

pin to the 0.6V

reference. When the load current increases, the V

volt-

age decreases slightly below the reference. This

LTC3407-2

sn34072 34072fs

decrease causes the error amplifier to increase the I

voltage until the average inductor current matches the new
load current.

The main control loop is shut down by pulling the RUN pin
to ground.

Low Current Operation

Two modes are available to control the operation of the
LTC3407-2 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.

To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407-2
automatically switches into Burst Mode operation, in
which the PMOS switch operates intermittently based on
load demand with a fixed peak inductor current. By run-
ning cycles periodically, the switching losses which are
dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
hysteretic voltage comparator trips when I

is below

0.35V, shutting off the switch and reducing the power. The
output capacitor and the inductor supply the power to the
load until I

exceeds 0.65V, turning on the switch and the

main control loop which starts another cycle.

For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3407-2 continues
to switch at a constant frequency down to very low
currents, where it will begin skipping pulses. The effi-
ciency in pulse skip mode can be improved slightly by
connecting the SW node to the MODE/SYNC input which
reduces the clock frequency by approximately 30%.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal p-channel MOSFET and the inductor.

An important design consideration is that the R

DS(ON)

the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407-2 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica-
tions Information Section).

Low Supply Operation

To prevent unstable operation, the LTC3407-2 incorpo-
rates an Under-Voltage Lockout circuit which shuts down
the part when the input voltage drops below about 1.65V.

OPERATIO

APPLICATIO S I FOR ATIO

A general LTC3407-2 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, C

and C

OUT

can

be selected.

Inductor Selection

Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current I

decreases with

higher inductance and increases with higher V

or V

OUT

Accepting larger values of I

allows the use of low

inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
I

= 0.3 · I

LIM

, where I

LIM

is the peak switch current limit.

The largest ripple current I

occurs at the maximum

input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:

OUT

IN MAX

(

)

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation

LTC3407-2

sn34072 34072fs

Table 1. Representative Surface Mount Inductors

PART

VALUE

DCR

MAX DC

SIZE

NUMBER

(µH)

( MAX)

CURRENT (A) W × L × H (mm

)

Sumida

2.2

0.075

1.20

3.8 × 3.8 × 1.8

CDRH3D16

3.3

0.110

1.10

4.7

0.162

0.90

Sumida

1.5

0.068

0.900

3.2 × 3.2 × 1.2

CDRH2D11

2.2

0.170

0.780

Sumida

2.2

0.116

0.950

4.4 × 5.8 × 1.2

CMD4D11

3.3

0.174

0.770

Murata

1.0

0.060

1.00

2.5 × 3.2 × 2.0

LQH32CN

2.2

0.097

0.79

Toko

2.2

0.060

1.08

2.5 × 3.2 × 2.0

D312F

3.3

0.260

0.92

Panasonic

3.3

0.17

1.00

4.5 × 5.4 × 1.2

ELT5KT

4.7

0.20

0.95

Output Capacitor (C

OUT

) Selection

The selection of C

OUT

is driven by the required ESR to

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (V

OUT

) is deter-

mined by:

I ESR

f C

OUT

where f = operating frequency, C

OUT

= output capacitance

and I

= ripple current in the inductor. The output ripple

is highest at maximum input voltage since I

increases

with input voltage. With I

= 0.3 · I

LIM

the output ripple

will be less than 100mV at maximum V

and f

= 2.25MHz

with:

ESR

COUT

< 150m

Once the ESR requirements for C

OUT

have been met, the

RMS current rating generally far exceeds the I

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
num electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages. The
OS-CON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer

begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
increase.

Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don't radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI require-
ments than on what the LTC3407-2 requires to operate.
Table 1 shows some typical surface mount inductors that
work well in LTC3407-2 applications.

Input Capacitor (C

) Selection

In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately V

OUT

. To prevent large voltage transients, a low equivalent

series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:

RMS

MAX

OUT

(

)

where the maximum average output current I

MAX

equals

the peak current minus half the peak-to-peak ripple cur-
rent, I

MAX

= I

LIM

/2.

This formula has a maximum at V

= 2V

OUT

, where I

RMS

= I

OUT/2

. This simple worst-case is commonly used to

design because even significant deviations do not offer
much relief. Note that capacitor manufacturer's ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on V

for high frequency decoupling, when not

using an all ceramic capacitor solution.

APPLICATIO S I FOR ATIO

LTC3407-2

sn34072 34072fs

capacitors, such as Sanyo POSCAP, Panasonic Special
Polymer (SP), and Kemet A700, offer very low ESR, but
have a lower capacitance density than other types. Tanta-
lum capacitors have the highest capacitance density, but
they have a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies. An
excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a signifi-
cantly larger ESR, and are often used in extremely cost-
sensitive applications provided that consideration is given
to ripple current ratings and long term reliability. Ceramic
capacitors have the lowest ESR and cost, but also have the
lowest capacitance density, a high voltage and tempera-
ture coefficient, and exhibit audible piezoelectric effects.
In addition, the high Q of ceramic capacitors along with
trace inductance can lead to significant ringing.

In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3407-2 in parallel with the
main capacitors for high frequency decoupling.

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop "zero" at 5kHz to 50kHz that is instrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which

APPLICATIO S I FOR ATIO

Figure 2. LTC3407-2 General Schematic

RUN2

= 2.5V

TO 5.5V

OUT2

OUT1

RUN1

POR

SW1

FB1

GND

FB2

SW2

MODE/SYNC

LTC3407-2

POWER-ON
RESET

OUT2

OUT1

3407 F02

PS*

BM*

*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V

: Burst Mode

requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, AVX,
Kemet, TDK, and Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V

pin. At best, this ringing can

couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, V

DROOP

, is usually

about 2-3 times the linear drop of the first cycle. Thus, a
good place to start is with the output capacitor size of
approximately:

OUT

DROOP

2 5

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.

Setting the Output Voltage

The LTC3407-2 develops a 0.6V reference voltage be-
tween the feedback pin, V

, and the ground as shown in

Figure 2. The output voltage is set by a resistive divider
according to the following formula:

LTC3407-2

sn34072 34072fs

Hot Swap is registered trademark of Linear Technology Corporation.

OUT

0 6

Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-forward ca-
pacitor C

may also be used. Great care should be taken to

route the V

line away from noise sources, such as the

inductor or the SW line.

Power-On Reset

The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 2

clock cycles (about 117ms).

This delay can be significantly longer in Burst Mode
operation with low load currents, since the clock cycles
only occur during a burst and there could be milliseconds
of time between bursts. This can be bypassed by tying the
POR output to the MODE/SYNC input, to force pulse
skipping mode during a reset. In addition, if the output
voltage faults during Burst Mode sleep, POR could have a
slight delay for an undervoltage output condition and may
not respond to an overvoltage output. This can be avoided
by using pulse skipping mode instead. When either chan-
nel is shut down, the POR output is pulled low, since one
or both of the channels are not in regulation.

Mode Selection & Frequency Synchronization

The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V

enables Burst Mode operation, which

provides the best low current efficiency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.

The LTC3407-2 can also be synchronized to an external
2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse skipping and the
top switch turn-on is synchronized to the rising edge of the
external clock.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V

OUT

immediately shifts by an amount

equal to I

LOAD

· ESR, where ESR is the effective series

resistance of C

OUT

. I

LOAD

also begins to charge or

discharge C

OUT

, generating a feedback error signal used

by the regulator to return V

OUT

to its steady-state value.

During this recovery time, V

OUT

can be monitored for

overshoot or ringing that would indicate a stability
problem.

The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor, C

can be added to improve the high frequency response, as
shown in Figure 2. Capacitor C

provides phase lead by

creating a high frequency zero with R2, which improves
the phase margin.

The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.

In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input
capacitors. The discharged input capacitors are effectively
put in parallel with C

OUT

, causing a rapid drop in V

OUT

. No

regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap

controller is

designed specifically for this purpose and usually incorpo-
rates current limiting, short-circuit protection, and soft-
starting.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would

APPLICATIO S I FOR ATIO

LTC3407-2

sn34072 34072fs

produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% - (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407-2 circuits: 1)V

quiescent current, 2)

switching losses, 3) I

R losses, 4) other losses.

1) The V

current is the DC supply current given in the

Electrical Characteristics which excludes MOSFET driver
and control currents. V

current results in a small (<0.1%)

loss that increases with V

, even at no load.

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from V

ground. The resulting dQ/dt is a current out of V

that is

typically much larger than the DC bias current. In continu-
ous mode, I

GATECHG

= f

+ Q

), where Q

and Q

are the

gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V

and thus their effects will be more pronounced at higher
supply voltages.

3) I

R losses are calculated from the DC resistances of the

internal switches, R

, and external inductor, R

. In

continuous mode, the average output current flows through
inductor L, but is "chopped" between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R

DS(ON)

and the duty cycle (DC) as follows:

= (R

DS(ON)TOP

)(DC) + (R

DS(ON)BOT

)(1 DC)

The R

DS(ON)

for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics
curves. Thus, to obtain I

R losses:

R losses = I

OUT2

+ R

)

4) Other `hidden' losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to

include these "system" level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3407-2 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3407-2 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.

To prevent the LTC3407-2 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:

RISE

= P

where P

is the power dissipated by the regulator and

is the thermal resistance from the junction of the die to the
ambient temperature.

The junction temperature, T

, is given by:

= T

RISE

+ T

AMBIENT

As an example, consider the case when the LTC3407-2 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the R

DS(ON)

resistance of the

main switch is 0.425. Therefore, power dissipated by
each channel is:

= I

· R

DS(ON)

= 272mW

The MS package junction-to-ambient thermal resistance,

, is 45°C/W. Therefore, the junction temperature of the

APPLICATIO S I FOR ATIO

LTC3407-2

sn34072 34072fs

Figure 3. LTC3407-2 Layout Diagram (See Board Layout Checklist)

RUN2

OUT2

OUT1

RUN1

POR

SW1

FB1

GND

FB2

SW2

MODE/SYNC

LTC3407-2

OUT2

OUT1

3407 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

regulator operating in a 70°C ambient temperature is
approximately:

= 2 · 0.272 · 45 + 70 = 94.5°C

which is below the absolute maximum junction tempera-
ture of 125°C.

Design Example

As a design example, consider using the LTC3407-2 in an
portable application with a Li-Ion battery. The battery
provides a V

= 2.8V to 4.2V. The load requires a maxi-

mum of 800mA in active mode and 2mA in standby mode.
The output voltage is V

OUT

= 2.5V. Since the load still

needs power in standby, Burst Mode operation is selected
for good low load efficiency.

First, calculate the inductor value for about 30% ripple
current at maximum V

MHz

2 5

2 25

300

2 5

4 2

1 5

Choosing a vendor's closest inductor value of 2.2µH,
results in a maximum ripple current of:

MHz

2 5

2 25

2 2

2 5

4 2

204

· .

For cost reasons, a ceramic capacitor will be used. C

OUT

selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

MHz

OUT

2 5

800

2 25

2 5

7 1

· ( %· .

)

A good standard value is 10µF. Since the output imped-
ance of a Li-Ion battery is very low, C

is typically 10µF.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.

The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.

Figure 1 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3407-2. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout:

1. Does the capacitor C

connect to the power V

(Pin 3)

and GND (exposed pad) as close as possible? This capaci-
tor provides the AC current to the internal power MOSFETs
and their drivers.

2. Are the C

OUT

and L1 closely connected? The () plate of

OUT

returns current to GND and the () plate of C

3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C

OUT

and a ground sense line

terminated near GND (exposed pad). The feedback signals
V

should be routed away from noisy components and

traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.

4. Keep sensitive components away from the SW pins. The
input capacitor C

and the resistors R1 to R4 should be

routed away from the SW traces and the inductors.

5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of C

or C

OUT

6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to V

or GND.

APPLICATIO S I FOR ATIO

LTC3407-2

sn34072 34072fs

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1664)

MSOP (MSE) 0603

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 0.27

(.007 .011)

TYP

0.127 ± 0.076

(.005 ± .003)

0.86

(.034)

REF

0.50

(.0197)

BSC

1 2 3 4 5

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

7 6

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010)

0° 6° TYP

DETAIL "A"

GAUGE PLANE

5.23

(.206)

MIN

3.20 3.45

(.126 .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

2.083 ± 0.102

(.082 ± .004)

2.794 ± 0.102

(.110 ± .004)

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.83 ± 0.102

(.072 ± .004)

2.06 ± 0.102

(.081 ± .004)

3.00 ±0.10

(4 SIDES)

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.38 ± 0.10

BOTTOM VIEW--EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

2.38 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

0.00 0.05

(DD10) DFN 0403

0.25 ± 0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)

2.15 ±0.05

0.50
BSC

0.675 ±0.05

3.50 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3407-2

sn34072 34072fs

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

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3407 TA05

OUT

= 3.3V

Burst Mode OPERATION
NO LOD ON OTHER CHANNEL

4.2V

2.8V

3.6V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

1000

3407 TA06

OUT

= 1.8V

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NO LOAD ON OTHER CHANNEL

4.2V

2.8V

3.6V

Efficiency vs Load Current

RUN2

= 2.8V

TO 4.2V

OUT2

= 3.3V

AT 200mA

OUT1

= 1.8V

AT 800mA

RUN1

POR

SW1

FB1

GND

FB2

SW2

MODE/SYNC

LTC3407-2

C1
10µF

R5
100k

POWER-ON
RESET

C4, 22pF

C5, 22pF

2.2µH

10µH

887k

604k

R1
301k

196k

C3
10µF

C6
47µF

C2
10µF

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TYPICAL APPLICATIO

Part Number LTC3407-2