ispLSI

2064E

In-System Programmable

SuperFASTTM High Density PLD

2064e_05

Description

The ispLSI 2064E is a High Density Programmable Logic
Device. The device contains 64 Registers, 64 Universal
I/O pins, four Dedicated Input Pins, three Dedicated
Clock Input Pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2064E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2064E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.

The basic unit of logic on the ispLSI 2064E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Functional Block Diagram

Copyright Š 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2000

Features

ˇ SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC
-- 2000 PLD Gates
-- 64 I/O Pins, Four Dedicated Inputs
-- 64 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- 100% Functionally and JEDEC Upward Compatible

with ispLSI 2064 Devices

ˇ HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 200 MHz Maximum Operating Frequency

pd = 4.5 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- 5V Programmable Logic Core
-- ispJTAGTM In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

-- User-Selectable 3.3V or 5V I/O Supports Mixed

Voltage Systems

-- PCI Compatible Outputs
-- Open-Drain Output Option
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- Unused Product Term Shutdown Saves Power

ˇ ispLSI OFFERS THE FOLLOWING ADDED FEATURES

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

ˇ OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to

Minimize Switching Noise

-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

ˇ ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

GLB

Logic

Array

D Q

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

0139/2064E

Specifications

ispLSI 2064E

Functional Block Diagram

Figure 1. ispLSI 2064E Functional Block Diagram

TDO/IN 2

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

CLK 0

CLK 1

CLK 2

GOE 0

I/O 0
I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14
I/O 15

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41
I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

TDI/IN 0

TMS/IN 1

I/O 4

I/O 5

BSCAN

RESET

0139B(1)isp/2064E

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

Input Bus

Output Routing Pool (ORP)

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

Output Routing Pool (ORP)

Megablock

Input Bus

GOE 1

TCK/IN 3

Generic Logic

Blocks (GLBs)

The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each
ispLSI 2064E device contains two Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2064E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2064E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.

Specifications

ispLSI 2064E

Absolute Maximum Ratings

Supply Voltage V

cc ...................................................

-0.5 to +7.0V

Input Voltage Applied .............................. -2.5 to V

+1.0V

Off-State Output Voltage Applied ........... -2.5 to V

+1.0V

Storage Temperature ..................................... -65 to 150

Case Temp. with Power Applied .................... -55 to 125

Max. Junction Temp. (T

) with Power Applied ............ 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

Erase/Reprogram Specification

Capacitance (TA=25

C, f=1.0 MHz)

SYMBOL

Table 2-0006/2064e

PARAMETER

I/O Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input Capacitance

V = 5.0V, V = 2.0V

I/O

Clock Capacitance

V = 5.0V, V = 2.0V

= 0

C to +70

SYMBOL

Table 2-0005/2096E

PARAMETER

Supply Voltage: Logic Core, Input Buffers

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

4.75

2.0

5.25

0.8

CCIO

Supply Voltage: Output Drivers

4.75

5.25

3.3V

3.0

3.6

Table 2-0008/2064e

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10,000

Cycles

Specifications

ispLSI 2064E

Output Load Conditions (see Figure 2)

Figure 2. Test Load

+ 5V

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

DC Electrical Characteristics

Over Recommended Operating Conditions

Input Pulse Levels

Table 2-0003/2064E

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 2

3-state levels are measured 0.5V from
steady-state active level.

1.5 ns

TEST CONDITION

470

390

35pF

390

35pF

470

390

35pF

Active High

Active Low

470

390

5pF

390

5pF

Active Low to Z
at V +0.5V

Active High to Z
at V -0.5V

Table 2-0004/2064

Switching Test Conditions

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Unused inputs held at 0.0V.
5. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I

Table 2-0007/2064E

PARAMETER

IL-PU

2,4,5

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current

Operating Power Supply Current

= 8 mA

= -4 mA

(Max.)

= 0.0V, V

= 3.0V

CONDITION

MIN.

TYP.

MAX. UNITS

2.4

0.4

-10

Input or I/O High Leakage Current

CCIO

5.25V

CCIO

- 0.2)V

CCIO

I/O Active Pull-Up Current

2.0V

-10

-250

Output Short Circuit Current

CCIO

= 5.0V or 3.3V, V

OUT

= 0.5V

-240

100

TOGGLE

= 1 MHz

Specifications

ispLSI 2064E

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-200

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

Table 2-0030A/2064E

1
tsu2 + tco1

( )

-135

MIN.

MAX.

DESCRIPTION

PARAMETER

Data Prop Delay, 4PT Bypass, ORP Bypass

4.5

7.5

pd2

Data Prop Delay

max

Clk Freq with Internal Feedback

200

135

MHz

max (Ext.)

Clk Freq with External Feedback

MHz

max (Tog.)

Clk Frequency, Max. Toggle

MHz

su1

GLB Reg Setup Time before Clk, 4 PT Bypass

co1

GLB Reg Clk to Output Delay, ORP Bypass

GLB Reg Hold Time after Clk, 4 PT Bypass

0.0

su2

GLB Reg Setup Time before Clk

4.5

co2

10 GLB Reg Clk to Output Delay

11 GLB Reg Hold Time after Clk

0.0

12 External Reset Pin to Output Delay

rw1

13 External Reset Pulse Duration

3.5

ptoeen

14 Input to Output Enable

ptoedis

15 Input to Output Disable

goeen

16 Global OE Output Enable

goedis

17 Global OE Output Disable

18 External Synch Clk Pulse Duration, High

2.5

19 External Synch Clk Pulse Duration, Low

2.5

133

200

3.5

3.0

3.5

6.0

8.0

4.0

7.0

100

143

5.0

0.0

6.0

0.0

5.0

3.5

10.0

4.0

4.5

10.0

12.0

7.0

-100

MIN. MAX.

10.0

100

0.0

8.0

0.0

6.5

5.0

100

6.5

5.0

6.0

13.5

15.0

9.0

13.0

Part Number ispLSI 2064E

Document Outline