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1
3/19/04
IRLR7833
IRLU7833
HEXFET
®
Power MOSFET
Notes
through
are on page 11
Applications
Benefits
l
Very Low RDS(on) at 4.5V V
GS
l
Ultra-Low Gate Impedance
l
Fully Characterized Avalanche Voltage
and Current
l
High Frequency Synchronous Buck
Converters for Computer Processor Power
l
High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
D-Pak
IRLR7833
I-Pak
IRLU7833
V
DSS
R
DS(on)
max
Qg
30V
4.5m
:
33nC
Absolute Maximum Ratings
Parameter
Units
V
DS
Drain-to-Source Voltage
V
V
GS
Gate-to-Source Voltage
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
A
I
DM
Pulsed Drain Current
P
D
@T
C
= 25°C
Maximum Power Dissipation
g
W
P
D
@T
C
= 100°C
Maximum Power Dissipation
g
Linear Derating Factor
W/°C
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
1.05
R
JA
Junction-to-Ambient (PCB Mount)
gÃ
50
°C/W
R
JA
Junction-to-Ambient
110
300 (1.6mm from case)
10 lbf
x
in (1.1N
x
m)
Max.
140
f
99
f
560
± 20
30
-55 to + 175
140
0.95
71
PD - 94547A
IRLR/U7833
2
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S
D
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BV
DSS
Drain-to-Source Breakdown Voltage
30
V
V
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
19
mV/°C
R
DS(on)
Static Drain-to-Source On-Resistance
3.6
4.5
m
4.4
5.5
V
GS(th)
Gate Threshold Voltage
1.4
2.3
V
V
GS(th)
/
T
J
Gate Threshold Voltage Coefficient
-6.0
mV/°C
I
DSS
Drain-to-Source Leakage Current
1.0
µA
150
I
GSS
Gate-to-Source Forward Leakage
100
nA
Gate-to-Source Reverse Leakage
-100
gfs
Forward Transconductance
66
S
Q
g
Total Gate Charge
33
50
Q
gs1
Pre-Vth Gate-to-Source Charge
8.7
Q
gs2
Post-Vth Gate-to-Source Charge
2.1
nC
Q
gd
Gate-to-Drain Charge
13
Q
godr
Gate Charge Overdrive
9.9
See Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
15
Q
oss
Output Charge
22
nC
t
d(on)
Turn-On Delay Time
14
t
r
Rise Time
6.9
t
d(off)
Turn-Off Delay Time
23
ns
t
f
Fall Time
15
C
iss
Input Capacitance
4010
C
oss
Output Capacitance
950
pF
C
rss
Reverse Transfer Capacitance
470
Avalanche Characteristics
Parameter
Units
E
AS
Single Pulse Avalanche Energy
d
mJ
I
AR
Avalanche Current
Ã
A
E
AR
Repetitive Avalanche Energy
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
140
f
(Body Diode)
A
I
SM
Pulsed Source Current
560
(Body Diode)
Ãh
V
SD
Diode Forward Voltage
1.0
V
t
rr
Reverse Recovery Time
39
58
ns
Q
rr
Reverse Recovery Charge
37
55
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
Conditions
14
Max.
530
20
= 1.0MHz
I
D
= 12A
V
DS
= 16V
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 15A
f
V
GS
= 4.5V, I
D
= 12A
f
V
GS
= 20V
V
GS
= -20V
V
DS
= 15V, I
D
= 12A
V
DS
= 16V, V
GS
= 0V
V
DD
= 15V, V
GS
= 4.5V
f
T
J
= 25°C, I
F
= 12A, V
DD
= 15V
di/dt = 100A/µs
f
T
J
= 25°C, I
S
= 12A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
MOSFET symbol
V
GS
= 4.5V
Typ.
I
D
= 12A
V
GS
= 0V
V
DS
= 15V
Clamped Inductive Load
IRLR/U7833
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3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
2.25V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM
2.25V
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
2.25V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM
2.25V
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
0.10
1.00
10.00
100.00
1000.0
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
)
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
N
o
r
m
a
l
i
z
e
d
)
ID = 30A
VGS = 10V
IRLR/U7833
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
10
20
30
40
50
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
VDS= 24V
VDS= 15V
ID= 12A
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
I S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
IRLR/U7833
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5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
-75
-50
-25
0
25
50
75
100 125 150 175
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
V
G
S
(
t
h
)
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
ID = 250µA
25
50
75
100
125
150
175
0
25
50
75
100
125
150
I
,
D
r
ai
n C
u
rrent
(A)
°
D
LIMITED BY PACKAGE
T
C
, Case Temperature (°C)
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
1
Notes:
1. Duty factor D =
t / t
2. Peak T
= P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
T
her
m
a
l R
e
s
pons
e
(
Z
)
1
th
JC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRLR/U7833
6
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D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
µ
F
50K
.2
µ
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
RG
IAS
0.01
tp
D.U.T
L
VDS
+
-
VDD
DRIVER
A
15V
20V
V
GS
Fig 14a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 14b. Switching Time Waveforms
V
DS
Pulse Width 1 µs
Duty Factor 0.1 %
R
D
V
GS
R
G
D.U.T.
V
GS
+
-
V
DD
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
2500
5000
7500
10000
12500
15000
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
ID
TOP 8.2A
14A
BOTTOM 20A
IRLR/U7833
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7
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
· Low Stray Inductance
· Ground Plane
· Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
· dv/dt controlled by R
G
· Driver same type as D.U.T.
· I
SD
controlled by Duty Factor "D"
· D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
IRLR/U7833
8
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
= I
rms
2
× R
ds(on )
(
)
+ I ×
Q
gd
i
g
× V
in
× f
+ I ×
Q
gs 2
i
g
× V
in
× f
+ Q
g
× V
g
× f
(
)
+
Q
oss
2
×V
in
× f
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
= P
conduction
+ P
drive
+ P
output
*
P
loss
= I
rms
2
× R
ds(on)
(
)
+ Q
g
× V
g
× f
(
)
+
Q
oss
2
× V
in
× f
+ Q
rr
× V
in
× f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs' susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss
Characteristic
IRLR/U7833
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9
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
TO-252AA (D-Pak) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X
0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
4.57 (.180)
2.28 (.090)
2X
1.14 (.045)
0.76 (.030)
1.52 (.060)
1.15 (.045)
1.02 (.040)
1.64 (.025)
5.46 (.215)
5.21 (.205)
1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D I U @ S I 6 U D P I 6 G
G P B P
S @ 8 U D A D @ S
, 5 ) 8
$
G P U Ã 8 P 9 @
6 T T @ H 7 G `
@ Y 6 H Q G @ )
X D U C Ã 6 T T @ H 7 G `
U C D T Ã D T Ã 6 I Ã D S A S !
` @ 6 S Ã ( Ã 2 Ã ( ( (
9 6 U @ Ã 8 P 9 @
G D I @ Ã 6
X @ @ F Ã %
D I Ã U C @ Ã 6 T T @ H 7 G ` Ã G D I @ Ã Å 6 Å
6 T T @ H 7 G @ 9 Ã P I Ã X X Ã % Ã ( ( (
G P U Ã 8 P 9 @ Ã ! " #
Q 6 S U Ã I V H 7 @ S
IRLR/U7833
10
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
6.22 (.245)
5.97 (.235)
- B -
3X
0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.28 (.090)
1.14 (.045)
0.76 (.030)
5.46 (.215)
5.21 (.205)
1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
9.65 (.380)
8.89 (.350)
2X
3X
2.28 (.090)
1.91 (.075)
1.52 (.060)
1.15 (.045)
4
1 2 3
6.45 (.245)
5.68 (.224)
0.58 (.023)
0.46 (.018)
IRLR/U7833
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11
Repetitive rating; pulse width limited by
max. junction temperature.
Starting T
J
= 25°C, L = 2.6mH, R
G
= 25
,
I
AS
= 20A.
Pulse width
400µs; duty cycle
2%.
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR
TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
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