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February 1996
COPYRIGHT
INTEL CORPORATION 1996
Order Number 271116-005
M87C196KC M87C196KD
16-BIT HIGH-PERFORMANCE CHMOS
MICROCONTROLLERS WITH ON-CHIP EPROM
Special Environment
M87C196KC
16 KBytes EPROM
512 Bytes RAM
M87C196KD
32 KBytes EPROM 1024 Bytes RAM
Y
M87C196KC 16 MHz Operation
Y
M87C196KD 16 and 20 MHz Operation
Y
Register-to-Register Architecture
Y
28 Interrupt Sources 16 Vectors
Y
Peripheral Transaction Server
Y
1 4 ms 16 x 16 Multiply (20 MHz)
Y
1 75 ms 16 x 16 Multiply (16 MHz)
Y
2 4 ms 32 16 Divide (20 MHz)
Y
3 0 ms 32 16 Divide (16 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I O Ports
Y
16-Bit Watchdog Timer
Y
Available in 68-Lead PGA and 68-Lead
Ceramic Quad Flatpack Packages
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I O Subsystem
Y
16-Bit Timer
Y
16-Bit Up Down Counter with Capture
Y
3 Pulse-Width-Modulated Outputs
Y
Four 16-Bit Software Timers
Y
8- or 10-Bit A D Converter with
Sample Hold
Y
HOLD HLDA Bus Protocol
Y
Product Grades
SE1 (QML)
b
55 C to
a
125 C
SE2 (QML)
b
40 C to
a
125 C
(M87C196KD only)
The M87C196KC KD 16-bit microcontroller is a high performance member of the MCS -96 microcontroller
family The M87C196KC KD is an enhanced M80C196KB device with on-chip RAM and EPROM Intel's
CHMOS III-E process provides a high performance processor along with low power consumption
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter
For bus design information configuration and programming please see the 8XC196KC 8XC196KD User's
Manual (order
272238)
MCS -96 is a registered trademark of Intel Corporation
M87C196KC M87C196KD
PIN DESCRIPTIONS
Symbol
Name and Function
V
CC
Main supply voltage (5V)
V
SS
Digital circuit ground (0V) There are three V
SS
pins all of which must be connected
V
REF
Reference voltage for the A D converter (5V) V
REF
is also the supply voltage to the analog
portion of the A D converter and the logic used to read Port 0 Must be connected for A D
and Port 0 to function
ANGND
Reference ground for the A D converter Must be held at nominally the same potential as
V
SS
V
PP
Timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to
V
SS
and a 1 MX resistor to V
CC
If this function is not used V
PP
may be tied to V
CC
This pin
is the programming voltage on the EPROM device
XTAL1
Input of the oscillator inverter and of the internal clock generator
XTAL2
Output of the oscillator inverter
CLKOUT
Output of the internal clock generator The frequency of CLKOUT is
the oscillator
frequency
RESET
Reset input to the chip
BUSWIDTH
Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus
cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an
8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus
NMI
A positive transition causes a vector through 203EH
INST
Output high during an external memory read indicates the read is an instruction fetch INST
is valid throughout the bus cycle INST is activated only during external memory accesses
and output low for a data fetch
EA
Input for memory select (External Access) EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM EA equal to
a TTL-low causes accesses to those locations to be directed to off-chip memory
ALE ADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a signal to demultiplex the address from the address data bus When the pin is
ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during
external memory accesses
RD
Read signal output to external memory RD is activated only during external memory reads
WR WRL
Write and Write Low output to external memory as selected by the CCR WR will go low for
every external write while WRL will go low only for external writes where an even byte is
being written WR WRL is activated only during external memory writes
BHE WRH
Bus High Enable or Write High output to external memory as selected by the CCR BHE e
0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0
selects the bank of memory that is connected to the low byte of the data bus Thus
accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the
high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is
selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH
is valid only during 16-bit external memory write cycles
5
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