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March 1995
COPYRIGHT
INTEL CORPORATION 1996
Order Number 271276-002
M80C186XL20 16 12 10
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Y
Low Power Full Static Version of
M80C186
Y
Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
Compatible Mode
NMOS 80186 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y
Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y
Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y
Speed Versions Available
20 MHz (M80C186XL20)
16 MHz (M80C186XL16)
12 5 MHz (M80C186XL12)
10 MHz (M80C186XL)
Y
Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y
Complete System Development
Support
All 8086 and 80C186 Software
Development Tools Can Be Used for
M80C186XL System Development
ASM 86 Assembler PL M-86
Pascal-86 Fortran-86 iC-86 and
System Utilities
In-Circuit-Emulator (ICE
TM
-186)
Y
Available in 68-Pin
Ceramic Pin Grid Array (PGA)
Y
Military Temperature Range
b
55 C to
a
125 C (T
C
)
The Intel M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor It offers higher
speed and lower power consumption than the standard M80C186 but maintains 100% clock-for-clock func-
tional compatibility Packaging and pinout are also identical
271276 1
M80C186XL20 16 12 10
16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR
CONTENTS
PAGE
INTRODUCTION
10
M80C186XL BASE ARCHITECTURE
10
M80C186XL Clock Generator
10
Bus Interface Unit
11
M80C186XL PERIPHERAL
ARCHITECTURE
11
Chip-Select Ready Generation Logic
11
DMA Unit
12
Timer Counter Unit
12
Interrupt Control Unit
12
Enhanced Mode Operation
12
Queue-Status Mode
12
DRAM Refresh Control Unit
13
Power-Save Control
13
Interface for 80C187 Math
Coprocessor
13
ONCE Test Mode
13
ABSOLUTE MAXIMUM RATINGS
14
DC CHARACTERISTICS
14
CONTENTS
PAGE
AC CHARACTERISTICS
16
Major Cycle Timings (Read Cycle)
16
Major Cycle Timings (Write Cycle)
18
Major Cycle Timings (Interrupt
Acknowledge Cycle)
20
Software Halt Cycle Timings
22
Clock Timings
23
Ready Peripheral and Queue Status
Timings
25
Reset and Hold HLDA Timings
27
AC TIMING WAVEFORMS
33
EXPLANATION OF THE AC
SYMBOLS
36
DERATING CURVES
37
M80C186XL EXECUTION TIMINGS
38
INSTRUCTION SET SUMMARY
39
FOOTNOTES
44
2
M80C186XL
Table 1 M80C186XL Pin Description
Symbol
PGA
Type
Name and Function
Pin No
V
CC
9
I
System Power a5 volt power supply
43
I
V
SS
26
I
System Ground
60
I
RESET
57
O
RESET Output indicates that the M80C186XL CPU is being reset and
can be used as a system reset It is active HIGH synchronized with
the processor clock and lasts an integer number of clock periods
corresponding to the length of the RES signal Reset goes inactive 2
clockout periods after RES goes inactive When tied to the TEST
BUSY pin RESET forces the M80C186XL into enhanced mode
RESET is not floated during bus hold
X1
59
I
Crystal Inputs X1 and X2 provide external connections for a
fundamental mode or third overtone parallel resonant crystal for the
X2
58
O
internal oscillator X1 can connect to an external clock instead of a
crystal In this case minimize the capacitance on X2 The input or
oscillator frequency is internally divided by two to generate the clock
signal (CLKOUT)
CLKOUT
56
O
Clock Output provides the system with a 50% duty cycle waveform
All device pin timings are specified relative to CLKOUT CLKOUT is
active during reset and bus hold
RES
24
I
An active RES causes the M80C186XL to immediately terminate its
present activity clear the internal logic and enter a dormant state
This signal may be asynchronous to the M80C186XL clock The
M80C186XL begins fetching instructions approximately 6
clock
cycles after RES is returned HIGH For proper initialization V
CC
must
be within specifications and the clock signal must be stable for more
than 4 clocks with RES held LOW RES is internally synchronized
This input is provided with a Schmitt-trigger to facilitate power-on RES
generation via an RC network
TEST BUSY
47
I O
The TEST pin is sampled during and after reset to determine whether
the M80C186XL is to enter Compatible or Enhanced Mode Enhanced
Mode requires TEST to be HIGH on the rising edge of RES and LOW
four CLKOUT cycles later Any other combination will place the
M80C186XL in Compatible Mode During power-up active RES is
required to configure TEST BUSY as an input A weak internal pullup
ensures a HIGH state when the input is not externally driven
TEST
In Compatible Mode this pin is configured to operate as TEST
This pin is examined by the WAIT instruction If the TEST input is
HIGH when WAIT execution begins instruction execution will
suspend TEST will be resampled every five clocks until it goes LOW
at which time execution will resume If interrupts are enabled while the
M80C186XL is waiting for TEST interrupts will be serviced
BUSY
In Enhanced Mode this pin is configured to operate as
BUSY The BUSY input is used to notify the M80C186XL of Math
Coprocessor activity Floating point instructions executing in the
M80C186XL sample the BUSY pin to determine when the Math
Coprocessor is ready to accept a new command BUSY is active
HIGH
5
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