SLE 66CLX640P Short Product Information

Ref.: SPI_SLE66CLX640P_0404.doc

This document contains preliminary information on a new product under development.
Details are subject to change without notice.
Revision History:

Current Version 2004-04-27

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Important: Further information is confidential and on request. Please contact:

Infineon Technologies AG in Munich, Germany,
Security & Chip Card ICs,
Tel +49 - (0)89 234-80000

Fax +49 - (0)89 234-81000
E-Mail: security.chipcard.ics@infineon.com

Published by Infineon Technologies AG, SMS Security Applications Group
St.-Martin-Strasse 53, D-81541 München
Š Infineon Technologies AG 2004
All Rights Reserved.

To our valued customers
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The information herein is given to describe certain components and shall not be considered as warranted
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circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon
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Due to technical requirements components may contain dangerous substances. For information on the types in
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Infineon Technologies Components may only be used in life-support devices or systems with the express written
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that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices
or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect
human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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16-Bit High Security Dual Interface Controller
ISO/IEC 7816 and 14443 Type A &B Compliant Interfaces
For Contact and Contactless Operation with MMU in 0.22 ľm CMOS Technology
136-Kbyte ROM, 5-Kbyte RAM, 64-Kbyte EEPROM
1100-Bit Advanced Crypto Engine supporting RSA and Elliptic Curve GF (p) and
112-Bit / 192-Bit DDES-EC2 Accelerator
supporting DES, 3DES and Elliptic Curve GF (2n)

Features

Enhanced low power 8051 CPU with
extended addressing modes for dual
interface smart card applications

Instruction set opcode compatible with
standard 8051 processor with additional
powerful instructions optimized for smart
card application

Enhanced architecture with execution
time 6 times faster (18 times using
PLLmax) than standard 8051 processor at
same external clock

134 Kbytes User ROM for operating
system and application (programs & data)

2 Kbytes reserved ROM for Resource
Management System (RMS_E) with
Contactless Optimized EEPROM
write/erase routines

64 Kbytes Secure EEPROM in
SuperSlim technology for application
program and data

4k bytes XRAM, 700 bytes Crypto-RAM
and 256 bytes internal RAM for fast data
processing

Memory Management Unit

Certified True Random Number
Generator

Dual Key Triple DES (DDES) &
GF

) Elliptic Curve (EC2) Accelerator

Advanced Crypto Engine for Elliptic
Curve GF(p) and up to 2048 bits RSA
computation

CRC Module according to ISO/IEC 3309
supporting CCIT v.41 & HDLC X25

8 Interrupt Vectors Module with 3 priority
levels to ensure real time operation

PLL: to speed up the internal CPU clock
frequency up to 15MHz (optional use)

Two 16-bit Timers with interrupt capability
for protocols, security checks & watch dog
implementations

Power saving sleep mode

Temperature range:
contact-based: -25°C to +85°C
contact-less: -25°C to +70°C

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Full operation either via Contact-based
and/or Contactless interfaces
controlled by Operating System
enhances Security Level

Contact-based Interface

Contact configuration and serial
interface according to ISO/IEC 7816

UART handling serial interface compliant
with ISO/IEC 7816 supporting
transmission protocols T=0 and T=1

Supply voltage range:
5V ą 10% (Class A)
3V ą 10% (Class B)

Current consumption < 10 mA @ 5.5 V

External CPU clock frequency:
1 to 7.5 MHz

Internal CPU clock frequency:
up to 15 MHz

ESD protection larger than 6 kV

Contactless Interface

Interface according to ISO/IEC 14443 for
both Type A and Type B

Carrier frequency 13.56 MHz

Data rate
106 Kbit/s in type A operation
up to 848 Kbit/s in type B operation

Anticollision & Transmission Protocol
supported by open source application
notes for both Type A & B

Flexible Internal CPU clock frequency:
fully configurable from 1.7MHz up to
15 MHz

256 bytes buffer for contactless data
exchange (FiFo circular architecture)

Parallel operation of CPU, Peripherals
like DES, CRC and Contactless Interface
possible for High Demanding
Contactless Applications

EEPROM (SuperSlim Technology)

Byte wise EEPROM programming and read
accesses

Versatile & Flexible page mode for 1 to 256
bytes write/erase operation

32 bytes security area including:
- 16 bytes chip unique identification number
- 16 bytes PROM area (OTP like)

Fast personalisation mode 1.5 ms

Typical Page Erase time < 2.5ms

Typical Page Writing time < 1.8 ms

Minimum of 100.000 Write/erase cycles

Data retention for a minimum of 10 years

EEPROM programming voltage generated
on chip

Memory Management and Protection
Unit

Addressable memory up to 1 Mbytes

Separates OS (system mode) and
Application (application mode)

System routines called by traps

Access Restrictions to peripherals in
application mode controlled by OS

Code execution from XRAM possible

Values are temperature dependant

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Security Features

Operation state monitoring mechanism

The chip goes in a secure reset state on any
following sensors alarm:

Low and high voltage sensors

Internal voltage sensor

Frequency sensors and filters

Light sensor

Glitch sensor

Temperature sensor

Life Test Sensor

Internal power-on reset sensor

Active Shield with automatic and user
controlled attack detection

Secure chip and firmware design

Security scrambled & optimized chip
layout against physical chip manipulation

Memory encryption/decryption module
(MED) for XRAM, ROM and EEPROM
against reverse engineering and power
attacks

ROM code not visible due to implantation

Mask dependant ROM code encrypted
during production

Chip Unique encryption of the XRAM and
EEPROM

Flexible encryption of part or whole
EEPROM by additional user-defined key

16 byte Unique chip identification number
for anti-clone countermeasure & tracking

16 bytes security PROM hardware
protected (OTP like)

Secure start of the operating system
ensured by certified Self Test Software
(STS)

Certified EEPROM programming routines
(RMS_E)

True Random Number Generator with
Firmware test function

High Speed SPA/DPA resistant Triple
DES (DDES) Accelerator and Advanced
Crypto Engine

Anti Snooping

HW-countermeasures against SPA/DPA-,
Timing- and DFA-attacks (differential fault
analysis)

Supported Standards

ISO/IEC 7816

EMV 2000

GSM 11.1x

ETSI TS 102 221

ISO/IEC 14443

ISO/IEC 3309

CCIT v.41

HDLC X25

Part Number SLE66CLX640P