1
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q
5
R
D
Q
Q /
2
Q
O E/RS T
0
1
1
0
/2
V CO
LO O P
FILTER
PH ASE
D ETEC TO R
1
0
FREQ _S EL
RE F_SE L
LO CK
FEEDBA CK
SYNC
0
SYNC
1
P LL_EN
2xQ
PE
JULY 2000
2000 Integrated Device Technology, Inc.
DSC-5823/1
c
QS5919
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
·
5V operation
·
Low noise CMOS level outputs
·
< 500ps output skew, Q
0
Q
4
·
2xQ output, Q outputs, Q output, Q/2 output
·
Outputs 3-state and reset while OE/RST low
·
PLL disable feature for low frequency testing
·
Internal loop filter RC network
·
Functional equivalent to Motorola MC88915
·
Positive or negative edge synchronization (PE)
·
Balanced drive outputs ±36mA
·
160MHz maximum frequency (2xQ output)
·
Available in QSOP and PLCC packages
DESCRIPTION
The QS5919 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight outputs
are available: 2xQ, Q
0
-Q
4
, Q
5
, Q/2. Careful layout and design ensure
< 500ps skew between the Q
0
-Q
4
, and Q/2 outputs. The QS5919 includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5919 is designed for use in high-
performance workstations, multi-board computers, networking hard-
ware, and mainframe systems. Several can be used in parallel or
scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
2
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max.
Unit
AV
DD
/V
DD
Supply Voltage to Ground
0.5 to +7
V
V
IN
DC Input Voltage V
IN
0.5 to +7
V
Maximum Power
QSOP
655
mW
Dissipation (T
A
= 85°C)
PLCC
770
mW
T
STG
Storage Temperature Range
65 to +150
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
° C, f = 1MHz, V
IN
= 0V)
QSOP
PLCC
Parameter
Typ.
Max.
Typ.
Max.
Unit
C
IN
3
4
4
6
pF
PLCC
TOP VIEW
20
19
18
15
16
23
22
24
21
17
V
DD
GND
PLL_EN
GND
Q/2
Q
3
LOCK
V
DD
2xQ
Q
1
25
28
27
26
V
DD
Q
2
GND
Q
4
2
3
1
9
10
AV
DD
PE
OE/RST
SYNC
0
FEEDBACK
AGND
5
6
7
4
8
Q
5
11
12
FREQ_SEL
SYNC
1
GND
V
DD
REF_SEL
13
14
Q
0
GND
O
E
/
R
S
T
V
D
D
Q
5
G
N
D
Q
4
V
D
D
2
x
Q
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
P
L
L
_
E
N
G
N
D
Q
1
V
D
D
Q
0
G
N
D
F
R
E
Q
_
S
E
L
FEEDBACK
REF_SEL
SYNC
0
AV
DD
PE
AGND
SYNC
1
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
3
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC
0
I
Reference clock input
SYNC
1
I
Reference clock input
REF_SEL
I
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
FEEDBACK
I
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Q
0
-Q
4
O
Clock outputs
Q
5
O
Clock output. Matched in frequency, but inverted with respect to Q.
2xQ
O
Clock output. Matched in phase, but frequency is double the Q frequency.
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
LOCK
O
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to
the inputs.
OE/RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL_EN
I
PLL enable. Enables and disables the PLL. Useful for testing purposes.
PE
I
When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the
negative edge of SYNC.
V
DD
--
Power supply for output buffers.
AV
DD
--
Power supply for phase lock loop and other internal circuitries.
GND
--
Ground supply for output buffers.
AGND
--
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= 40°C to +85°C, AV
DD
/V
DD
= 5.0V ± 10%
Symbol
Description
55
70
100
133
160
Units
F
MAX_2XQ
Max Frequency, 2xQ
55
70
100
133
160
MHz
F
MAX_Q
Max Frequency, Q
0
- Q
4
, Q
5
27.5
35
50
66.5
80
MHz
F
MAX_Q/2
Max Frequency, Q/2
13.75
17.5
25
33.25
40
MHz
F
MIN_2XQ
Min Frequency, 2xQ
20
20
20
20
20
MHz
F
MIN_Q
Min Frequency, Q
0
- Q
4
, Q
5
10
10
10
10
10
MHz
F
MIN_Q/2
Min Frequency, Q/2
5
5
5
5
5
MHz
4
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
Output Used for
SYNC (MHz)
(allowable range)
(1)
Output Frequency Relationships
(2)
FREQ_SEL
Feedback
Min.
Max
Q/2
Q
5
Q
0
- Q
4
2XQ
HIGH
Q/2
F
MIN_Q/2
F
MAX _Q/2
SYNC
SYNC X 2
SYNC X 2
SYNC X 4
HIGH
Q
0
-Q
4
F
MIN_Q
F
MAX _Q
SYNC / 2
SYNC
SYNC
SYNC X 2
HIGH
Q
5
F
MIN_Q
F
MAX _Q
SYNC / 2
SYNC
SYNC
SYNC X 2
HIGH
2xQ
F
MIN_2XQ
F
MAX _2XQ
SYNC / 4
SYNC / 2
SYNC / 2
SYNC
LOW
Q/2
F
MIN_Q/2
/2
F
MAX _Q/2
/2
SYNC
SYNC X 2
SYNC X 2
SYNC X 4
LOW
Q
0
-Q
4
F
MIN_Q
/2
F
MAX _Q
/2
SYNC / 2
SYNC
SYNC
SYNC X 2
LOW
Q
5
F
MIN_Q
/2
F
MAX _Q
/2
SYNC / 2
SYNC
SYNC
SYNC X 2
LOW
2xQ
F
MIN_2XQ
/2
F
MAX _2XQ
/2
SYNC / 4
SYNC / 2
SYNC / 2
SYNC
NOTES:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_2
X
Q
. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect
output frequencies.
2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40°C to +85°C, AV
DD
/V
DD
= 5.0V ± 10%
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
--
--
0.8
V
V
OH
Output HIGH Voltage
I
OH
=
-36mA
V
DD
0.75
--
--
V
I
OH
=
-100µA
V
DD
0.2
--
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 36mA
--
--
0.45
V
V
DD
= Min., I
OL
= 100
µA
--
--
0.2
V
V
H
Input Hysteresis
--
--
100
--
mV
I
OZ
Output Leakage Current
V
OUT
= V
DD
or GND, V
DD
= Max.
--
--
5
µA
I
IN
Input Leakage Current
V
IN
= AV
DD
or GND, AV
DD
= Max.
--
--
5
µA
I
PD
Input Pull-Down Current (PE)
AV
DD
= Max., V
IN
= AV
DD
--
--
100
µA
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DD
= Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
1.5
mA
I
DD
Power Supply Current per Input HIGH
V
DD
= Max., V
IN
= 3.4V
0.4
1.5
mA
I
DDD
Dynamic Power Supply Current
(1)
V
DD
= Max., C
L
= 0pF
0.2
0.4
mA/MHz
NOTE:
1. Relative to the frequency of Q outputs.
5
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INPUT TIMING REQUIREMENTS
Symbol
Description
(1)
Min.
Max.
Unit
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
--
3
ns
F
I
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
2.5
F
MAX _2XQ
MHz
t
PWC
Input clock pulse, HIGH or LOW
(2)
2
--
ns
D
H
Duty cycle, SYNC
0
, SYNC
1
(2)
25
75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
(1)
Min.
Max.
Unit
t
SKR
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(2)
--
500
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/2
(2)
--
500
ps
t
SKALL
Output Skew, All Outputs
(2,5)
--
750
ps
t
PW
Pulse Width, 2xQ output, >40MHz
T
CY
/2
- 0.4
T
CY
/2 + 0.4
ns
t
PW
Pulse Width, Q
0
-Q
4
, Q
5,
Q/2 outputs, 80MHz
T
CY
/2
- 0.4
T
CY
/2 + 0.4
ns
t
J
Cycle-to-Cycle Jitter
(4)
- 0.15
0.15
ns
t
PD
SYNC Input to Feedback Delay
(6)
- 500
0
ps
t
LOCK
SYNC to Phase Lock
--
10
ms
t
PZH
t
PZL
Output Enable Time, OE/RST LOW to HIGH
(3)
0
14
ns
t
PHZ
t
PLZ
Output Disable Time, OE/RST HIGH to LOW
(3)
0
14
ns
t
R,
t
F
Output Rise/Fall Times, 0.2V
DD
0.8V
DD
0.3
2.5
ns
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. Skew measured at selected synchronization edge.
6. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
6
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
1.0ns
1.0ns
2.0V
0.8V
3.0V
0V
V
th
= 1.5V
t
P W
t
R
t
F
C ON TR OL
IN PU T
EN A BLE
DISABLE
3V
1.5V
0V
3.5V
V
O L
0V
t
P Z L
1.5V
D D
O UTPUT
NO R MALLY
LO W
O UTPUT
N OR M ALLY
HIG H
SW ITCH
OP EN
SW ITC H
C LO SED
0.3V
0.3V
t
P Z H
t
PLZ
t
P H Z
V
O H
300
30pF
7.0V
OU TP UT
V
D D
OU TP UT
300
100
100
0V
0.5V
D D
0.8V
D D
0.2V
D D
V
D D
1.5V
D D
AC TEST LOADS AND WAVEFORMS
TEST CIRCUIT 1
TTL INPUT TEST WAVEFORM
CMOS OUTPUT WAVEFORM
TEST CIRCUIT 2
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
7
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
t
J
t
SK F
t
SKA LL
t
S KR
t
P D
SYNC
FE EDBA CK
Q
Q
0
-Q
4
Q /2
2xQ
Q
5
AC TIMING DIAGRAM
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK and
PE
= GND. For
PE
= V
DD
, the negative edge of FEEDBACK aligns with the
negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.
2. All parameters except t
PD
are measured at 0.5V
DD
; t
PD
is measured at 1.5V.
8
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5919 provides
for replication of incoming SYNC clock signals. Any manipulation of that
signal, such as frequency multiplying or inversion is performed by digital
logic following the PLL (see the block diagram). The key advantage of the
SIMPLIFIED DIAGRAM OF QS5919 FEEDBACK
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back, it
will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output will
optimally have zero phase shift with respect to the input. In fact, the internal
loop filter on the QS5919 typically provides within 150ps of phase shift
between input and output.
PLL circuit is to provide an effective zero propagation delay between the
output and input signals. In fact, adding delay circuits in the feedback path,
`propagation delay' can even be negative! A simplified schematic of the
QS5919 PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q
Q/
2
Q
VCO
/2
/2
PHASE
DETECTO R
INPU T
2xQ
9
INDUSTRIAL TEMPERATURE RANGE
QS5919
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
5919
Low Skew CMOS PLL Clock Driver
with Integrated Loop Filter
QS
XX
Speed
XXXX
Device Type
X
Package
55
70
100
133
160
55MHz Max. Frequency
70MHz Max. Frequency
100MHz Max. Frequency
133MHz Max. Frequency
160MHz Max. Frequency
Q
J
Quarter Size Outline Package
Plastic Leaded Chip Carrier
X
Process
Blank
Industrial (-40°C to +85°C)
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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