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Part Number 29FCT2052T

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INDUSTRIAL TEMPERATURE RANGE
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
1
MAY 2001
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2001 Integrated Device Technology, Inc.
DSC-5502/1
FEATURES:
· A, B, and C grades
· Low input and output leakage


1µA (max.)
· CMOS power levels
· True TTL input and output compatibility:
­ V
OH
= 3.3V (typ.)
­ V
OL
= 0.3V (typ.)
· High Drive outputs (-15mA I
OH
, 48mA I
OL
)
· Meets or exceeds JEDEC standard 18 specifications
· Power off disable outputs permit "live insertion"
· Available in SOIC and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT29FCT2052AT/BT/CT
FAST CMOS
OCTAL REGISTERED
TRANSCEIVER
DESCRIPTION:
The IDT29FCT2052T is an 8-bit registered transceiver built using an
advanced dual metal CMOS technology. Two 8-bit back-to-back registers
store data flowing in both directions between two bidirectional buses.
Separate clock, clock enable and 3-state output enable signals are provided
for each register. Both A outputs and B outputs are guaranteed to sink 64mA.
The IDT29FCT2052T has balanced drive outputs with current limiting
resistors. This offers low ground bounce, minimal undershoot and con-
trolled output fall times-reducing the need for external series terminating
resistors. The IDT29FCT2052T is a plug-in replacement for the IDT29FCT52T.
A
1
A
2
A
4
A
5
A
6
A
7
A
3
A
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
D
1
D
2
D
4
D
5
D
6
D
7
D
3
D
0
CE
CP
A
Reg.
Q
1
Q
2
Q
4
Q
5
Q
6
Q
7
Q
3
Q
0
D
1
D
2
D
4
D
5
D
6
D
7
D
3
D
0
CE
CP
B
Reg.
Q
1
Q
2
Q
4
Q
5
Q
6
Q
7
Q
3
Q
0
OEA
CPB
CEB
OEB
CPA
CEA
INDUSTRIAL TEMPERATURE RANGE
2
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
­0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
­0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
­65 to +150
°C
I
OUT
DC Output Current
­60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
2
3
1
20
19
18
15
16
A
6
A
7
A
1
A
0
A
2
A
5
A
3
A
4
23
22
24
21
17
V
CC
13
14
OEA
CPB
CEB
9
10
B
6
B
7
5
6
7
4
8
B
2
B
0
B
1
B
3
B
4
B
5
11
12
CEA
GND
OEB
CPA
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
= LOW-to-HIGH Transition
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
Inputs
Internal
D
CP
CE
Q
Function
X
X
H
N C
Hold Data
L
L
L
Load Data
H
L
H
OUTPUT CONTROL
(1)
Internal
OE
Q
Y-Outputs
Function
H
X
Z
Disable Outputs
L
L
L
Enable Outputs
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
±1
µA
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
±1
µA
I
OZH
High Impedance Output Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
I
= 2.7V
--
--
±1
µA
I
OZL
(3-State Output pins)
(4)
V
I
= 0.5V
--
--
±1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
±1
µA
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= ­18mA
--
­0.7
­1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= 3V
--
0.01
1
µA
V
IN
= GND or V
CC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= ­40°C to +85°C, V
CC
= 5.0V ±5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= ­55°C.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
16
48
--
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
-16
-48
--
mA
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= ­15mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 12mA
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
OUTPUT DRIVE CHARACTERISTICS
PIN DESCRIPTION
Name
I/O
Description
A
0-7
I/O
Eight bidirectional lines carrying the A Register inputs or B Register outputs
B
0-7
I/O
Eight bidirectional lines carrying the B Register inputs or A Register outputs
CPA
I
Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal.
CEA
I
Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When
CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
OEB
I
Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B
0-7
lines. When OEB is HIGH, the B
0-7
outputs
are in the high-impedance state.
CPB
I
Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal.
CEB
I
Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When
CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
OEA
I
Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A
0-7
lines. When OEA is HIGH, the A
0-7
outputs
are in the high-impedance state.
INDUSTRIAL TEMPERATURE RANGE
4
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
0.06
0.12
mA/
Current
(4)
Outputs Open
V
IN
= GND
MHz
OE
A
or OE
B
= GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
0.6
2.2
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE
A
or OE
B
= GND
V
IN
= 3.4V
--
1.1
4.2
One Bit Toggling
V
IN
= GND
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max.
V
IN
= V
CC
--
1.5
4
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE
A
or OE
B
= GND
V
IN
= 3.4V
--
3.8
13
(5)
Eight Bits Toggling
V
IN
= GND
at f
i
= 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Output Frequency
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
29FCT2052AT
29FCT2052BT
29FCT2052CT
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
2
10
2
7.5
2
6.3
ns
t
PHL
CPA, CPB to An, Bn
R
L
= 500
t
PZH
Output Enable Time
1.5
10.5
1.5
8
1.5
7
ns
t
PZL
OEA or OEB to An, Bn
t
PHZ
Output Disable Time
1.5
10
1.5
7.5
1.5
6.5
ns
t
PLZ
OEA or OEB to An, Bn
t
SU
Set-up Time, HIGH or LOW
2.5
--
2.5
--
2.5
--
ns
An, Bn to CPA, CPB
t
H
Hold Time, HIGH or LOW
2
--
1.5
--
1.5
--
ns
An, Bn to CPA, CPB
t
SU
Set-up Time, HIGH or LOW
3
--
3
--
3
--
ns
CEA, CEB to CPA, CPB
t
H
Hold Time, HIGH or LOW
2
--
2
--
2
--
ns
CEA, CEB to CPA, CPB
t
W
Clock Pulse Width HIGH or LOW
(3)
3
--
3
--
3
--
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
INDUSTRIAL TEMPERATURE RANGE
6
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
Pulse
G enerator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OU T
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
IN PUT
TIM ING
INPUT
ASYNC HR O NOU S C ON TROL
PRES ET
C LEAR
ETC.
SYN CH RON OUS C ONTR OL
t
S U
t
H
t
RE M
t
S U
t
H
H IGH-LOW -HIG H
PULSE
LOW -H IGH -LOW
PULSE
t
W
1.5V
1.5V
SAM E PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
1.5V
V
O H
t
PL H
O UTPUT
OPPOSITE PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
t
P LH
t
P H L
t
P H L
V
O L
C ONTR OL
INPU T
3V
1.5V
0V
3.5V
0V
OUTPU T
N ORM A LLY
LOW
OUTPU T
N ORM A LLY
H IGH
SW ITCH
CLO SE D
SW ITC H
OPEN
V
O L
0.3V
0.3V
t
PLZ
t
PZL
t
P ZH
t
PH Z
3.5V
0V
1.5V
1.5V
EN AB LE
DISA BLE
V
O H
PRES ET
C LEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
7
ORDERING INFORMATION
XX
FCT
IDT
Temp. Range
XXXX
Device Type
X
Package
SO
Q
52AT
52BT
52CT
Octal Registered Transceiver
29
- 40°C to +85°C
Small Outline IC
Quarter-size Small Outline Package
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com