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ICS951901

Integrated
Circuit
Systems, Inc.

0670B--07/15/04

Programmable Frequency Generator & Integrated Buffers for Pentium

III

Processor

Block Diagram

Recommended Application:
Single chip clock solution for IA platform.
Output Features:

3 - CPU @ 2.5V

13 - SDRAM @ 3.3V

6 - PCI @3.3V,

2 - AGP @ 3.3V

1 - 48MHz, @3.3V fixed.

1 - 24/48MHz, @3.3V selectable by I

(Default is 24MHz)

2 - REF @3.3V, 14.318MHz.

Features:
·

Programmable ouput frequency.

Programmable ouput rise/fall time.

Programmable SDRAM and CPU skew.

Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.

Watchdog timer technology to reset system
if over-clocking causes malfunction.

Uses external 14.318MHz crystal.

FS pins for frequency select

Skew Specifications:
·

CPU - CPU: < 175ps

SDRAM - SDRAM < 250ps (except SDRAM12)

PCI - PCI: < 500ps

CPU (early) - PCI: 1-4ns (typ. 2ns)

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull down to GND.

These are double strength.

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (2:0)

SDRAM (12:0)

PCICLK (4:0)

AGP (1:0)

PCICLK_F

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

PCI

DIVDER

Stop

SDATA

SCLK

FS(3:0)

PD#

PCI_STOP#

CPU_STOP#

SDRAM_STOP#

MODE

AGP_SEL

Control

Logic

Config.

Reg.

/ 2

REF(1:0)

AGP

DIVDER

VDDA

(AGPSEL)REF0

*(FS3)REF1

GND

X1
X2

VDDPCI

*(FS1)PCICLK_F

*(FS2)PCICLK0

PCICLK1
PCICLK2
PCICLK3
PCICLK4

GND

VDDAGP

AGPCLK0
AGPCLK1

GND
GND

*(FS0)48MHz

*(MODE)24_48MHz

VDD48

SDATA

SCLK

VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR

ICS9519

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FS3

FS2

FS1

FS0

CPU

SDRAM

PCI

AGP1

AGP0

Bit7

Bit6

Bit5

Bit4

MHz

SEL=1

SEL=0

66.67

33.33

66.67

100.00

33.33

66.67

133.34

33.33

66.67

75.00

37.50

75.00

83.31

33.32

66.64

90.00

30.00

60.00

95.00

31.67

63.33

100.00

66.67

33.33

66.67

100.00

33.33

66.67

100.00

133.34

33.33

66.67

105.00

35.00

70.00

112.00

33.60

67.20

117.99

35.40

70.80

124.09

31.02

62.05

133.34

100.00

33.33

66.67

133.34

33.33

66.67

Bit2

ICS951901

0670B--07/15/04

General Description

Pin Configuration

The ICS951901 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.

The ICS951901 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I

C interface as a vehicle for changing

output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.

Power Groups

Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF

MODE Pin Power Management Control Input

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 7, 15, 22, 25,

35, 43

VDD

PWR

3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output

AGPSEL

AGP frequency select pin.

REF0

OUT

14.318 MHz reference clock.

FS3

Frequency select pin.

REF1

OUT

14.318 MHz reference clock.

4, 14, 18, 19, 29,

32, 39, 44

GND

PWR

Ground pin for 3V outputs.

Crystal input,nominally 14.318MHz.

OUT

Crystal output, nominally 14.318MHz.

FS1

Frequency select pin.

PCICLK_F

OUT

PCI clock output, not affected by PCI_STOP#

FS2

Frequency select pin.

PCICLK0

OUT

PCI clock output.

13, 12, 11, 10

PCICLK (4:1)

OUT

PCI clock outputs.

17, 16,

AGP (1:0)

OUT

AGP outputs defined as 2X PCI. These may not be stopped.

FS0

Frequency select pin.

48MHz

OUT

48MHz output clock

MODE

Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode

24_48MHz

OUT

Clock output for super I/O/USB default is 24MHz

SDATA

I/O

Data pin for I

C circuitry 5V tolerant

SCLK

Clock pin of I

C circuitry 5V tolerant

CPU_STOP#

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode

SDRAM11

OUT

SDRAM clock output

PCI_STOP#

Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode

SDRAM10

OUT

SDRAM clock output

SDRAM9

OUT

SDRAM clock output

SDRAM_STOP#

Stops all SDRAM clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode

PD#

Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms

SDRAM8

OUT

SDRAM clock output

26 33, 34, 36,
37, 38, 40, 41,

SDRAM (12,

7:0)

OUT

SDRAM clock outputs

45, 46, 47

CPUCLK (2:0)

OUT

CPU clock outputs.

VDDL

PWR

Power pin for the CPUCLKs. 2.5V

ICS951901

0670B--07/15/04

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note: PWD = Power-Up Default

Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

C is a trademark of Philips Corporation

FS3

FS2

FS1

FS0

CPU

SDRAM

PCI

AGP1

AGP0

Spread %

PWD

Bit2

Bit7

Bit6

Bit5

Bit4

MHz

SEL=1

SEL=0

66.67

33.33

66.67

± 0.35% center spread

66.67

100.00

33.33

66.67

± 0.35% center spread

66.67

133.34

33.33

66.67

± 0.35% center spread

75.00

37.50

75.00

± 0.35% center spread

83.31

33.32

66.64

± 0.35% center spread

90.00

30.00

60.00

± 0.35% center spread

95.00

31.67

63.33

± 0.35% center spread

100.00

66.67

33.33

66.67

± 0.35% center spread

100.00

33.33

66.67

± 0.35% center spread

100.00

133.34

33.33

66.67

± 0.35% center spread

105.00

35.00

70.00

± 0.35% center spread

112.00

33.60

67.20

± 0.35% center spread

117.99

35.40

70.80

± 0.35% center spread

124.09

31.02

62.05

± 0.35% center spread

Bit 2

133.34

100.00

33.33

66.67

± 0.35% center spread

00000

Bit 7:4

133.34

33.33

66.67

± 0.35% center spread

Note1

75.00

100.00

37.50

75.00

± 0.35% center spread

75.00

112.50

32.14

64.29

± 0.35% center spread

75.00

150.00

32.14

64.29

± 0.35% center spread

83.31

111.07

33.32

66.64

± 0.35% center spread

83.32

166.65

31.25

62.49

± 0.35% center spread

90.00

60.00

30.00

60.00

± 0.35% center spread

90.00

120.00

30.00

60.00

± 0.35% center spread

95.00

63.33

31.67

63.33

± 0.35% center spread

95.00

126.66

31.67

63.33

± 0.35% center spread

105.00

70.00

35.00

70.00

± 0.35% center spread

105.00

140.00

35.00

70.00

± 0.35% center spread

112.00

84.00

33.60

67.20

± 0.35% center spread

117.99

88.49

35.40

70.80

± 0.35% center spread

124.09

93.07

31.02

62.05

± 0.35% center spread

129.99

97.49

32.50

64.99

± 0.35% center spread

140.00

105.00

35.00

70.00

± 0.35% center spread

Bit 3

0 - Frequency is selected by hardware select, Latched inputs

1 - Frequency is selected by Bit, 2 7:4

Bit 1

0 - Normal

1 - Spread Spectrum Enabled

Bit 0

0 - Running

1 - Tristate all outputs

Bit

Description

ICS951901

0670B--07/15/04

Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.

Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)

)

(

)

(

)

(

)

(

Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)

)

(

ICS951901

0670B--07/15/04

Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)

Byte 7: Vendor ID Register
(1= enable, 0 = disable)

)

(

)

(

)

(

)

(

)

(

)

(

Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)

Note: FS values in bit [0:4] will correspond to Byte 0 FS

values. Default safe frequency is same as 00000
entry in byte0.

Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register

Byte 9: Watchdog Timer Count Register

ICS951901

0670B--07/15/04

Notes:

1. PWD = Power on Default

Byte 11: VCO Frequency Control Register

Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .

Byte 12: VCO Frequency Control Register

Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.

Byte 13: Spread Sectrum Control Register

Byte 14: Spread Sectrum Control Register

Note: Please utilize software utility provided by ICS

Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.

Note: Please utilize software utility provided by ICS

Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.

Byte 15: Output Skew Control

Byte 16: Output Skew Control

)

(

)

(

ICS951901

0670B--07/15/04

Byte 17: Output Rise/Fall Time Select Register

Byte 18: Output Rise/Fall Time Select Register

)

(

Byte 19: Output Rise/Fall Time Select Register

Byte 20: Output Rise/Fall Time Select Register

)

(

VCO Programming Constrains

VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142

Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)

-0.5

To program the VCO frequency for over-clocking.

0. Before trying to program our clock manually, consider using ICS provided software utilities for easy

programming.

1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by

writing to byte 0, or using initial hardware power up frequency.

2. Write 0001, 1001 (19

) to byte 8 for readback of 21 bytes (byte 0-20).

3. Read back byte 11-20 and copy values in these registers.

4. Re-initialize the write sequence.

5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.

6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew

rate.

7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be

changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.

ICS951901

0670B--07/15/04

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V

+0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input High Voltage

+ 0.3

Input Low Voltage

- 0.3

0.8

Supply Current

=30 pF, CPU @ 66, 100 MHz

390

400

Power Down

300

600

Input frequency

= 3.3 V;

14.32

MHz

Input Capacitance

Logic Inputs

INX

X1 & X2 pins

Transition Time

trans

To 1st crossing of target Freq.

Settling Time

From 1st crossing to 1% target Freq.

Clk Stabilization

STAB

From V

= 3.3 V to 1% target Freq.

Skew

CPU-PCI

CPUV

= 1.5 V PCI V

=1.25V

1.9

Skew

CPU-SDRAM

CPUV

= 1.5 V SDRAM V

=1.25

-500

-300

Guaranteed by design, not 100% tested in production.

ICS951901

0670B--07/15/04

Electrical Characteristics - CPU

= 0 - 70°C; V

DDL

= 2.5 V +/-5%; VDDL = 2.5 V +/-5%; C

= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Output Impedance

DSP2B

= V

*(0.5)

Output Impedance

DSN2B

= V

*(0.5)

Output High Voltage

OH2B

= -12.0 mA

Output Low Voltage

OL2B

= 12 mA

0.4

Output High Current

OH2B

= 1.7 V

-19

Output Low Current

OL2B

= 0.7 V

Rise Time

r2B

= 0.4 V, V

= 2.0 V

0.4

1.2

1.6

Fall Time

f2B

= 2.0 V, V

= 0.4 V

0.4

1.1

1.6

Duty Cycle

t2B

= 1.25 V

46.9

Skew window

0:1

sk2B

= 1.25 V

175

Skew window

0:2

sk2B

= 1.25 V

142

375

Jitter, Cycle-to-cycle

jcyc-cyc

= 1.25 V, CPU=66 MHz

177

250

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - 24-48MHz

= 0 - 70°C; V

= 3.3 V +/-5%;VDDL = 2.5 V +/-5%; C

= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Output Impedance

DSP5B

= V

*(0.5)

Output Impedance

DSN5B

= V

*(0.5)

Output High Voltage

OH15

= -14 mA

2.4

Output Low Voltage

OL5

= 6.0 mA

0.4

Output High Current

OH5

= 2.0 V

-20

Output Low Current

OL5

= 0.8 V

Rise Time

= 0.4 V, V

= 2.4 V

0.4

1.45

Fall Time

= 2.4 V, V

= 0.4 V

0.4

1.5

Duty Cycle

= 1.5 V

52.5

Jitter

cycle to cycle

= 1.5 V

210

500

Guaranteed by design, not 100% tested in production.

ICS951901

0670B--07/15/04

Electrical Characteristics - PCI

= 0 - 70°C; V

= 3.3 V +/-5%; VDDL = 2.5 V +/-5%; C

= 10-30 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Output Impedance

DSP1B

= V

*(0.5)

Output Impedance

DSN1B

= V

*(0.5)

Output High Voltage

OH1

= -1 mA

2.4

Output Low Voltage

OL1

= 1 mA

0.55

Output High Current

OH1

OH @ MIN

= 1.0 V

-29

Output Low Current

OL1

OL @ MIN

= 1.95 V

Rise Time

= 0.4 V, V

= 2.4 V

0.5

2.3

2.5

Fall Time

= 2.4 V, V

= 0.4 V

0.5

2.3

2.5

Duty Cycle

= 1.5 V

51.2

Skew window

sk1

= 1.5 V

108

500

Jitter, Cycle-to-cycle

jcyc-cyc1

= 1.5 V

353

500

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - SDRAM

= 0 - 70°C; V

= 3.3 V +/-5%;VDDL = 2.5 V +/-5%; C

= 20-30 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Output Impedance

DSP3B

= V

*(0.5)

Output Impedance

DSN3B

= V

*(0.5)

Output High Voltage

OH3

= -18 mA

2.4

Output Low Voltage

OL3

= 9.4 mA

0.4

Output High Current

OH3

= 2.0 V

-46

Output Low Current

OL3

= 0.8V

Rise Time

= 0.4 V, V

= 2.4 V

0.8

1.6

Fall Time

= 2.4 V, V

= 0.4 V

0.8

1.6

Duty Cycle

= 1.5 V

48.5

Skew window

1(0:11)

sk3

= 1.5 V

192

250

Skew window

1( 0:12)

sk3

= 1.5 V

290

500

Jitter, Cycle-to-cycle

jcyc-cyc3

= 1.5 V, CPU=66,100,133 MHz

173

250

Guaranteed by design, not 100% tested in production.

ICS951901

0670B--07/15/04

Electrical Characteristics - AGP

= 0 - 70°C; V

=3.3V +/-5%; C

= 20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Output Impedance

DSP4B

*(0.5)

Output Impedance

DSN4B

*(0.5)

Output High Voltage

OH4B

= -18 mA

Output Low Voltage

OL4B

= 18 mA

0.4

Output High Current

OH4B

= 2.0 V

-19

Output Low Current

OL4B

= 0.8 V

Rise Time

r4B

= 0.4 V, V

= 2.4 V

0.5

1.5

Fall Time

f4B

= 2.4 V, V

= 0.4 V

0.5

1.6

Duty Cycle

t4B

= 1.5 V

52.3

Skew window1

tsk

= 1.5 V

55.5

175

Jitter Cyc-Cyc

tjcyc-cyc

= 1.5 V

239

500

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - REF

TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output High Voltage

OH5

= -12 mA

2.4

Output Low Voltage

OL5

= 9 mA

0.4

Output High Current

OH5

= 2.0 V

-22

Output Low Current

OL5

= 0.8 V

Rise Time

= 0.4 V, VOH = 2.4 V

1.8

Fall Time

= 2.4 V, VOL = 0.4 V

1.9

Duty Cycle

= 50%

54.5

Guaranteed by design, not 100% tested in production.

ICS951901

0670B--07/15/04

General I

C serial interface information for the ICS951901

How to Write:

· Controller (host) sends a start bit.
· Controller (host) sends the write address D2

(H)

· ICS clock will acknowledge
· Controller (host) sends a dummy command code
· ICS clock will acknowledge
· Controller (host) sends a dummy byte count
· ICS clock will acknowledge
· Controller (host) starts sending Byte 0 through Byte 28

(see Note 2)

· ICS clock will acknowledge each byte one at a time
· Controller (host) sends a Stop bit

How to Read:

· Controller (host) will send start bit.
· Controller (host) sends the read address D3

(H)

· ICS clock will acknowledge
· ICS clock will send the byte count
· Controller (host) acknowledges
· ICS clock sends Byte 0 through byte 6 (default)
· ICS clock sends Byte 0 through byte X (if X

(H)

was

written to byte 6).

· Controller (host) will need to acknowledge each byte
· Controller (host) will send a stop bit

*See notes on the following page

Controller (Host)

ICS (Slave/Receiver)

Start Bit

Address D2

(H)

ACK

Dummy Command Code

ACK

Dummy Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Byte 6

ACK

Byte 18

ACK

Byte 19

ACK

Byte 20

ACK

Stop Bit

How to Write:

Controller (Host)

ICS (Slave/Receiver)

Start Bit

Address D3

(H)

ACK

Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Byte 6

ACK

If 7

has been written to B6

Byte 7

ACK

If 1A

has been written to B6

Byte18

ACK

If 1B

has been written to B6

Byte 19

ACK

If 1C

has been written to B6

Byte 20

ACK

Stop Bit

How to Read:

ICS951901

0670B--07/15/04

The ICS clock generator is a slave/receiver, I

C component. It can read back the data stored in the latches

for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.

When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I

C interface, the protocol is set to use only Block-Writes from the

controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

At power-on, all registers are set to a default condition, as shown.

Notes:

Brief I

C registers description for ICS951901

Programmable System Frequency Generator

Register Name

Byte

Description

PWD Default

Functionality &
Frequency Select
Register

Output frequency, hardware / I

frequency select, spread spectrum &
output enable control register.

See individual
byte
description

Output Control Registers

1-6

Active / inactive output control
registers/latch inputs read back.

See individual
byte
description

Vendor ID & Revision ID
Registers

Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.

See individual
byte
description

Byte Count
Read Back Register

Writing to this register will configure
byte count and how many byte will

be read back. Do not write 00

this byte.

Watchdog Timer
Count Register

Writing to this register will configure
the number of seconds for the
watchdog timer to reset.

Watchdog Control
Registers

10 Bit [6:0]

Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.

000,0000

VCO Control Selection
Bit

10 Bit [7]

This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.

VCO Frequency Control
Registers

11-12

These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.

Depended on
hardware/byte
0 configuration

Spread Spectrum
Control Registers

13-14

These registers control the spread
percentage amount.

Depended on
hardware/byte
0 configuration

Group Skews Control
Registers

15-16

Increment or decrement the group
skew amount as compared to the
initial skew.

See individual
byte
description

Output Rise/Fall Time
Select Registers

17-20

These registers will control the
output rise and fall time.

See individual
byte
description

ICS951901

0670B--07/15/04

Fig. 1

Shared Pin Operation -
Input/Output Pins

The I/O pins designated by (input/output) on the ICS951901
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.

To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

8.2K

Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.

ICS951901

0670B--07/15/04

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94209. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is

synchronized to the CPU clocks inside the ICS94209.

3. All other clocks continue to run undisturbed. (including SDRAM outputs).

ICS951901

0670B--07/15/04

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS94209. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94209 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.

Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94209.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.

ICS951901

0670B--07/15/04

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.

Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.

Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

ICS951901

0670B--07/15/04

Ordering Information

ICS951901yFLF-T

INDEX

AREA

INDEX

AREA

1 2

h x 45°

SEATING

PLANE

SEATING

PLANE

- C -

.10 (.004) C

300 mil SSOP Package

MIN

MAX

MIN

MAX

2.41

2.80

.095

.110

0.20

0.40

.008

.016

0.20

0.34

.008

.0135

0.13

0.25

.005

.010

10.03

10.68

.395

.420

7.40

7.60

.291

.299

e
h

0.38

0.64

.015

.025

0.50

1.02

.020

.040

0°

8°

0°

8°

MIN

MAX

MIN

MAX

15.75

16.00

.620

.630

10-0034

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS

SEE VARIATIONS

0.635 BASIC

0.025 BASIC

Reference Doc.: JEDEC Publication 95, MO-118

VARIATIONS

SEE VARIATIONS

D mm.

D (inch)

Example:

Designation for tape and reel packaging

Lead Free (Optional)

Package Type
F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix
ICS = Standard Device

ICS XXXXXX y F LF- T

Part Number ICS951901