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Part Number ICS9248-192

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Integrated
Circuit
Systems, Inc.
ICS9248-192
0540E--08/20/03
Block Diagram
Frequency Timing Generator for Transmeta Systems
Pin Configuration
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
28-Pin TSSOP
Recommended Application:
Transmeta
Output Features:
·
1CPU(2.5V or 3.3V selectable) up to 66.6MHz &
overclocking of 66MHz.
·
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
·
1 REF (3.3V) at 14.318MHz.
·
1 48MHz (3.3V).
·
1 24_48MHz selectable output.
Features:
·
Supports Spread Spectrum modulation for CPU and
PCI clocks, default -0.4 downspread.
·
Efficient Power management scheme through stop
clocks and power down modes.
·
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
·
28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
·
CPU ­ CPU <175ps
·
PCI ­ PCI < 500ps
·
CPU(early) ­ PCI = 1.5ns ­ 4ns.
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
SDATA
SCLK
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#
ICS9248-192
1
2
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4
5
6
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9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SEL48_24#
CPU3.3V_2.5V#sel
SEL66/60#
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK0
PCICLK (5:0)
6
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
Control
Logic
Config.
Reg.
/ 2
REF
2
ICS9248-192
0540E--08/20/03
Pin Descriptions
Pin number
Pin name
Type
Description
1
GNDREF
Power
Ground for 14.318 MHz reference clock outputs
2
X1
Input
14.318 MHz crystal input
3
X2
Output
14.318 MHz crystal output
4
PD#
Input
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
12, 11, 10, 7, 6, 5
PCICLK (5:0)
Output
3.3V PCI clock outputs, free running selectable
8
GNDPCI
Power
Ground for PCI clock outputs
9
VDDPCI
Power
3.3V power for the PCI clock outputs
Sel48_24#
Input
Selects 24MHz (0) or 48MHz (1) output
24_48MHz
Output
Selectable output either 24MHz or 48MHz
13
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
14
SCLK
IN
Clock pin of I
2
C circuitry 5V tolerant
CPU3.3-2.5#
Input
3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
48MHz
Output
3.3V 48 MHz clock output, fixed frequency clock typically used with
USB devices
17
GND48
Power
Ground for 48 MHz clocks
18
VDD48
Power
3.3V power for 48/24 MHz clocks
19
SEL 66/60#
Input
Control for the frequency of clocks at the
CPU & PCICLK output pins.
"0" = 60 MHz. "1" = 66.6 MHz.
The PCI clock is multiplexed to run at 33.3 MHz
for both selected cases.
20
VDD_Core
Power
Isolated 3.3V power for core
21
GND_Core
Power
Isolated ground for core
22
PCI_Stop#
Input
Synchronous active low input used to stop the PCICLK in active low
state. It will not effect PCICLK_F or any other outputs.
23
CPUCLK0
Output
CPU clock outputs selectable 2.5V or 3.3V.
24
GNDLCPU
Power
Ground for CPU clock outputs
25
VDDLCPU
Power
2.5V or 3.3V power for CPU clock outputs
26
CPU_STOP#
Input
Asynchronous active low input pin used to stop the CPUCLK in
active low state, all other clocks will continue to run. The CPUCLK
will have a "Turnon " latency of at least 3 CPU clocks.
27
REF
Output
3.3V 14.318 MHz reference clock output
28
VDDREF
Power
3.3V power for 14.318 MHz reference clock outputs.
15
16
3
ICS9248-192
0540E--08/20/03
Power Management
ICS9248-192 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of
the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock
network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
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CPU Select Functions
#
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4
ICS9248-192
0540E--08/20/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
· Controller (host) sends a start bit.
· Controller (host) sends the write address D2
(H)
· ICS clock will acknowledge
· Controller (host) sends a dummy command code
· ICS clock will acknowledge
· Controller (host) sends a dummy byte count
· ICS clock will acknowledge
· Controller (host) starts sending first byte (Byte 0)
through byte 6
· ICS clock will acknowledge each byte one at a time.
· Controller (host) sends a Stop bit
How to Read:
· Controller (host) will send start bit.
· Controller (host) sends the read address D3
(H)
· ICS clock will acknowledge
· ICS clock will send the byte count
· Controller (host) acknowledges
· ICS clock sends first byte (Byte 0) through byte 6
· Controller (host) will need to acknowledge each byte
· Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
5
ICS9248-192
0540E--08/20/03
Bit2
Bit7
Bit6
Bit5
Bit4
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
60
30
-0.4 % down spread
0
0
0
0
1
60
30
-0.6 % down spread
0
0
0
1
0
60
30
-0.8 % down spread
0
0
0
1
1
60
30
-1.0 % down spread
0
0
1
0
0
66.6
33.3
-0.4 % down spread
0
0
1
0
1
66.6
33.3
-0.6 % down spread
0
0
1
1
0
66.6
33.3
-0.8 % down spread
0
0
1
1
1
66.6
33.3
-1.0 % down spread
0
1
0
0
0
67.32
33.66
2% over-clocking
0
1
0
0
1
68.64
34.32
4% over-clocking
0
1
0
1
0
69.96
34.98
6% over-clocking
0
1
0
1
1
72.6
36.3
10% over-clocking
0
1
1
0
0
61.5
30.75
over-clocking
0
1
1
0
1
63
31.5
over-clocking
0
1
1
1
0
64
32
over-clocking
0
1
1
1
1
65
32.5
over-clocking
Bit
1
0
0
0
0
60
30
+/- 0.5% center spread
2,7:4
1
0
0
0
1
66.6
33.3
+/- 0.5% center spread
1
0
0
1
0
50
25
under-clocking
1
0
0
1
1
48
24
under-clocking
1
0
1
0
0
58.8
29.4
2% under-clock
1
0
1
0
1
57.6
28.8
4% under-clock
1
0
1
1
0
56.4
28.2
6% under-clock
1
0
1
1
1
54
27
10% under-clock
1
1
0
0
0
60
30
-1.4 % down spread
1
1
0
0
1
60
30
-1.6 % down spread
1
1
0
1
0
60
30
-1.8 % down spread
1
1
0
1
1
60
30
-2.0 % down spread
1
1
1
0
0
66.6
33.3
-1.4 % down spread
1
1
1
0
1
66.6
33.3
-1.6 % down spread
1
1
1
1
0
66.6
33.3
-1.8 % down spread
1
1
1
1
1
66.6
33.3
-2.0 % down spread
Hardware latch inputs can only access these frequencies
0-Frequency is seleced by hardware select. Latched input
Bit1
0-Normal 1-Spread spectrun Enabled
0
Bit0
0-Running 1-Tristate all outputs
0
PWD
Bit
Bit3
0
00000
CPU
PCI
Spread %
1-Frequency is seleced by Bit 2, 7:4
Note: PWD = Power-Up Default
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap