Integrated Circuit Solution Inc.
1
SR004-0D
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
.EATURES
High-speed access times:
-- 8, 10, 12, 15, 20 ns
Automatic power-down when chip is deselected
CMOS low power operation
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
TTL compatible interface levels
Single 3.3V power supply
.ully static operation: no clock or refresh
required
Three-state outputs
DESCRIPTION
The
1+51
IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
1+51
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300mil SOJ and the 8*13.4mm TSOP-1 package.
IS61LV256
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
.UNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
256 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
IS61LV256
2
Integrated Circuit Solution Inc.
SR004-0D
PIN CON.IGURATION
28-Pin SOJ
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CON.IGURATION
8x13.4mm TSOP-1
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation Vcc Current
Not Selected
X
H
X
High-Z
I
SB
, I
SB
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Voltage Relative to GND
0.5 to +4.6
V
V
TERM
Terminal Voltage with Respect to GND
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
Com.
10 to +85
°C
Ind.
45 to +90
T
STG
Storage Temperature
65 to +150
°C
P
D
Power Dissipation
1
W
I
OUT
DC Output Current
±20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IS61LV256
Integrated Circuit Solution Inc.
3
SR004-0D
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
1
1
µA
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
Com.
1
1
µA
Ind.
5
5
Notes:
1. V
IL
(min.) = 0.3V (DC); V
IL
(min.) = 2.0V (pulse width
2.0 ns).
V
IH
(max.) = V
CC
+ 0.5V (DC); V
IH
(max.) = Vcc + 2.0V (pulse width
2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
p.
C
OUT
Output Capacitance
V
OUT
= 0V
5
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
OPERATING RANGE
Range
Ambient Temperature
Speed
V
CC
Commercial
0°C to +70°C
8, 10, 12
3.3V, +10%, 5%
15, 20
3.3V ± 10%
Industrial
40°C to +85°C
All
3.3V + 10%, 5%
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Sym. Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating V
CC
= Max., CE = V
IL
Com.
120
110
100
90
80
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
130
120
110
100
90
I
SB
TTL Standby Current
V
CC
= Max.,
Com.
25
25
25
25
25
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
30
30
30
30
30
CE
V
IH
, f = 0
I
SB
CMOS Standby
V
CC
= Max.,
Com.
2
2
2
2
2
mA
Current (CMOS Inputs)
CE
V
CC
0.2V,
Ind.
5
5
5
5
5
V
IN
> V
CC
0.2V, or
V
IN
0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61LV256
4
Integrated Circuit Solution Inc.
SR004-0D
AC TEST LOADS
.igure 1.
.igure 2.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and .all Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See .igures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
t
RC
Read Cycle Time
8
10
12
15
20
ns
t
AA
Address Access Time
8
10
12
15
20
ns
t
OHA
Output Hold Time
2
2
2
2
2
ns
t
ACE
CE Access Time
8
10
12
15
20
ns
t
DOE
OE Access Time
4
5
6
7
8
ns
t
LZOE
OE to Low-Z Output
0
0
0
0
0
ns
t
HZOE
OE to High-Z Output
4
5
5
6
6
ns
t
LZCE
CE to Low-Z Output
3
3
3
3
3
ns
t
HZCE
CE to High-Z Output
4
5
6
7
7
ns
t
PU
!
CE to Power-Up
0
0
0
0
0
ns
t
PD
"
CE to Power-Down
8
10
12
15
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
IS61LV256
Integrated Circuit Solution Inc.
5
SR004-0D
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL
.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVE.ORMS
READ CYCLE NO. 1
(1,2)
IS61LV256
6
Integrated Circuit Solution Inc.
SR004-0D
AC WAVE.ORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
t
WC
Write Cycle Time
8
10
12
15
20
ns
t
SCE
CE to Write End
7
8
8
10
12
ns
t
AW
Address Setup Time
7
8
8
10
12
ns
to Write End
t
HA
Address Hold
0
0
0
0
0
ns
from Write End
t
SA
Address Setup Time
0
0
0
0
0
ns
t
PWE
1
WE Pulse Width(OE High)
7
10
12
15
20
ns
t
PWE
2
WE Pulse Width(OE Low)
6.5
7
8
10
12
ns
t
SD
Data Setup to Write End
4.5
5
6
7
10
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
HZWE
!
WE LOW to High-Z Output
3.5
4
6
7
7
ns
t
LZWE
!
WE HIGH to Low-Z Output
0
0
0
0
0
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in .igure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
IS61LV256
Integrated Circuit Solution Inc.
7
SR004-0D
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE NO. 2
(WE Controlled, OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(WE Controlled, OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > V
IH
.
IS61LV256
8
Integrated Circuit Solution Inc.
SR004-0D
ORDERING IN.ORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
8
IS61LV256-8T
8*13.4mm TSOP-1
IS61LV256-8J
300mil SOJ
10
IS61LV256-10T
8*13.4mm TSOP-1
IS61LV256-10J
300mil SOJ
12
IS61LV256-12T
8*13.4mm TSOP-1
IS61LV256-12J
300mil SOJ
15
IS61LV256-15T
8*13.4mm TSOP-1
IS61LV256-15J
300mil SOJ
20
IS61LV256-15T
8*13.4mm TSOP-1
IS61LV256-20J
300mil SOJ
ORDERING IN.ORMATION
Industrial Range: 40°C to +85°C
Speed (ns)
Order Part No.
Package
8
IS61LV256-8TI
8*13.4mm TSOP-1
IS61LV256-8JI
300mil SOJ
10
IS61LV256-10TI
8*13.4mm TSOP-1
IS61LV256-10JI
300mil SOJ
12
IS61LV256-12TI
8*13.4mm TSOP-1
IS61LV256-12JI
300mil SOJ
15
IS61LV256-15TI
8*13.4mm TSOP-1
IS61LV256-15JI
300mil SOJ
20
IS61LV256-20TI
8*13.4mm TSOP-1
IS61LV256-20JI
300mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
.ax: 886-3-5783000
BRANCH O..ICE:
7., NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
.AX: 886-2-26962252
http://www.icsi.com.tw
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