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HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

This document is a general product description and is subject to change without notice. Hynix
Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent
licenses are implied.

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2003 Hynix Semiconductor Inc.

Contents

General Description ....................................................................................................................5

Features ....................................................................................................................................5

Block Diagram ...........................................................................................................................6

Pixel Structure ...........................................................................................................................7

Pin Diagram...............................................................................................................................8

Pin Diagram...............................................................................................................................9

Functional Description ..............................................................................................................10

Pixel Architecture ..............................................................................................................10

Sensor Imaging Operation ..................................................................................................10

On-chip Frequency Synthesizer ..........................................................................................11

11bit on-chip ADC..............................................................................................................11

Gamma Correction.............................................................................................................11

Color Interpolation..............................................................................................................12

Sub-sampling Mode ...........................................................................................................12

Scaling Mode ....................................................................................................................12

Color Correction.................................................................................................................12

Color Space Conversion & Reverse Color Space Conversion ..................................................13

Luminance Processing Contrast, Brightness adjustment ....................................................14

Chrominance Processing Saturation adjustment ................................................................14

Edge Enhancement ...........................................................................................................14

Chroma Suppression..........................................................................................................14

Automatic Flicker Cancellation............................................................................................14

Output Formatting..............................................................................................................15

Auto Exposure Control .......................................................................................................15

Auto White Balance...........................................................................................................15

Register Description .................................................................................................................16

Anti-Banding Configuration ........................................................................................................60

Frame Timing...........................................................................................................................60

Output Data according to Video Mode ........................................................................................66

Bayer Data Format ...................................................................................................................79

I2C Chip Interface.....................................................................................................................80

AC/DC Characteristics..............................................................................................................82

Electro-Optical Characteristics ..................................................................................................85

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General Description

HV7151SP is a highly integrated single chip CMOS color image sensor implemented by proprietary

Hynix 0.18um CMOS sensor process realizing high sensitivity and wide dynamic range. Active pixel

array is 1164x886. Each active pixel composed of 4 transistors, it has a micro-lens to enhance

sensitivity, and converts photon energy to analog pixel voltage. On-chip 11bit Analog to Digital

Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS)

scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions are

implemented to diversify its applications, and various output formats are supported for the sensor to

easily interface with different video codec chips. The integration of sensor function and image

processing functions make HV7151SP especially very suitable for mobile imaging systems such as

digital still camera, PC input camera and IMT-2000 phone's video part that requires very low power

and system compactness.

Features

Optical Format : 1/4 inch / Pixel Size : 3.2

m x 3.2

Active Pixel Array : 1170 x 886

Multiple Video Modes : 1152x864(MEGA), 640x480(VGA), 576x432(1/4 MEGA), 352x288(CIF),

320x240(QVGA), 288x216(1/16 MEGA), 176x144(QCIF)

Bayer RGB Color filter array / Micro-lens for high sensitivity

On-chip Frequency Synthesizer

On-chip 11 bit Analog to Digital Converter

Correlated Double Sampling (CDS) for reduction of Fixed Pattern Noise (FPN)

Automatic Flicker Cancellation (AFC)

Automatic Black Level Calibration (ABLC)

Gamma Correction by programmable piecewise linear approximation

5x5 Color Interpolation

Color Correction by programmable 3x3 matrix operation

Color Space Conversion from RGB to YCbCr and Reverse Conversion from YCbCr to RGB

Image adjustment :Contrast, Brightness, Saturation, Edge Enhancement, Chroma Suppression

Various Output Formats: CCIR-601, CCIR-656 Compatible

YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, RGB 565, Bayer

8bit/16bit Data Bus Mode

Automatic Exposure Control and Automatic White Balance Control

Power Save Mode

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Pin Diagram

C[7:0] should be set up as pull-up or pull-down when 8bit output mode is used.

Type

Symbol

Description

36-40, 1-3

Y[7:0]

Video Luminance Data[7:0]

DGNDI

Digital Ground for I/O Driver

DVDDI

1.8V Digital Power for I/O Driver

DVDDC

1.8V Power for Internal Digital Block

DGNDC

Ground for Internal Digital Block

8-15

C[7:0]

Video Chrominance Data[7:0]

DVDDIH

2.5V Digital Power for I/O Driver

DGNDIH Digital Ground for I/O Driver

SDA

I2C Standard data I/O port

SCK

I2C Clock Input

STROBE Strobe Signal Output

RESETB Sensor Reset, Low Active

ENB

Sensor sleep mode is controlled externally by this pin when

sleep mode register bit is low.

ENB low : sleep mode, ENB high : normal mode

DGNDI

Digital Ground for I/O Driver

DVDDI

1.8V Digital Power for I/O Driver

AVDDPH 2.5V Analog Power for Pixel Block

AGND

Analog Ground for Analog Block

AVDD

1.8V Power for Internal Analog Block

AINN

Analog Input Minus for Test ADC

AINP

Analog Input Plus for Test ADC

VSYNC

Video Frame Synchronization signal. VSYNC is active at start

of image data frame.

HSYNC

Video Horizontal Line Synchronization signal. Image data is

valid, when HSYNC is high.

VCLK

Video Output Clock

MCLK

Master Input Clock

DVDDIH

2.5V Digital Power for I/O Driver

DGNDI

Digital Ground for I/O Driver

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Functional Description

Pixel Architecture

Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer

transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible.

Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel

sensitivity is achieved.

ENB Setting guide information for normal stand-by mode

It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7151SP

after system power on

ex) If MCLK = 19.2[Mhz] and PLL 2x,

=> 2.68[Mcycle] / 38.4[MHz] = 69.79 ms

The time period of ENB high value have to keep for 69.79[ms] or more

Sensor Imaging Operation

Imaging operation is implemented by the offset mechanism of integration domain and scan

domain(rolling shutter scheme). First integration plane is initiated, and after the programmed

integration time is elapsed, scan plane is initiated, then image data start being produced.

DVDD/AVDD

RESETB

MCLK

VSYNC

I2C

ENB

Don

t care

Low

System power On

Initialization sequence

2.68 [

Mcycle

] for logic stable time

2.56 [

Mcycle

] for 1'st VSYNC out

More than 4cycle

Don

t care

1ms

Sensor operation sequence

Sensor Power down sequence

Camera Mode

Video stream

st VSYNC out

DVDD/AVDD

RESETB

MCLK

VSYNC

I2C

ENB

Don

t care

Low

System power On

Initialization sequence

More than 4cycle

Don

t care

1ms

Sensor operation sequence

Sensor Power down sequence

Camera Mode

Video stream

st VSYNC out

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Integration

Time

Frame 0

Time

Integration

Plane

Frame 0

Integration

Plane

Frame 1

Scan

Plane

Frame 0

Scan

Plane

Frame 1

Time

On-chip Frequency Synthesizer

On-chip Frequency Synthesizer generates variable frequency according to the proportion of

Reference(PREFDIV) to Feedback(PFDDIV) Divisor. Operating frequency is fully programmable and

output range is 5MHz to 100MHz.

11bit on-chip ADC

On-chip ADC converts analog pixel voltage to 11bit digital data.

Gamma Correction

Piecewise linear approximation method is implemented. Ten piece linear segments are supported and
user-programmable.

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Gamma Transfer Function

Out

Start 0

Start 1

128

256

384

512

1024

1536

3 2 64

Start 2

2047

Start 9

:
:

Color Interpolation

5x5 linear color interpolation is used to interpolate missing R, G, or B for mosaic image data from

pixel array. Interpolation is done by moving 5x5 interpolation window by one pixel horizontally and

vertically.

Sub-sampling Mode

The sub-sampling modes such as 1/4 sub-sampling and 1/16 sub-sampling are supported. The sub-

sampling sequence is as below. For example 1/4 sub-sampling, Row data are picked out from R,G,B

bayer raw data by the rate of four to two. And after 5x5 linear color interpolation, column data also are

picked out the rate of two to one. 1/16 sub-sampling is similar to 1/4 sub-sampling.

Scaling Mode

In addition to the sub-sampling mode, HV7151SP supports the scaling modes, such as 5/9 scaling

VGA, 5/18 scaling QVGA, 1/3 scaling CIF and 1/6 QCIF. Because HV7151SP normal image

size(1152x864) is not a multiple proportion of VGA/QVGA or CIF/QCIF image size, output data and

output clock of scaling mode are asymmetry.

Color Correction

Generally, the color spread effect is mainly caused by color filter characteristics. The effect is

compensated by 3x3 color correction operation. Color correction matrix may be resolved by

measuring sensor's color spread characteristics for primary color source and calculating the inverse

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matrix of color spread matrix. Nine registers for matrix coefficients are used in color correction

operation to get the optimal pure color. The relationship between input color and color-corrected color

is defined as below formula.

CRCM

where

R,G,B = Sensor color output

R',G',B' = Color-corrected output

Coefficients CRCMxx are programmable from 127/64 ~ 127/64. Programming register value for

intended color correction matrix coefficients should be resolved by the following equations.

For positive values, CRCMxx = Integer(Real Coefficient Value x 64);

For negative values, CRCMxx = Two's Complement(Integer(Real Coefficient Value x 64));

Real Coefficient Value values from 127/64 ~ 127/64 can be programmed.

Color Space Conversion & Reverse Color Space Conversion

Both of color space conversion and reverse color space conversion are implemented by 3x3 matrix

operation. Output ranges of color space conversion and reverse conversion are existed two modes.

One is 16

235, 16

Cb,Cr

240 & 16

reverse-R,G,B

235 and Another is 0

Y,Cb,Cr

255 & 0

reverse-R,G,B

255. These different modes are selected by control register.

For color space conversion and reverse conversion matrix, the equation from CCIR-601 standard is

normally used.

< Conversion Equation >

Mode 1 :

255

128

081

419

500

331

169

114

587

299

Range

Mode 2 :

240

235

128

071

368

439

291

148

098

504

257

Range

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In the above equations, R, G, and B are gamma-corrected values.

< Reverse Conversion Equation >

235

255

235

255

235

255

128

772

344

714

402

Range

Same matrix equations are applied to mode1 and mode2 in the reverse color space conversion. And

previously, output ranges 0 ~ 255 or 16 ~ 235 are decided by input ranges of Y,Cb,Cr.

Luminance Processing Contrast, Brightness adjustment

For contrast adjustment, Y digital channels are scaled by the contrast factor. Contrast factor

resolution is 1/128 and its range is 0 ~ 255/128.

For brightness adjustment, there is added a brightness factor to Y digital channels. Brightness factor

range is 128 ~ 127 and register value for brightness adjustment is following below.

For positive values, Brightness factor = Integer;

For negative values, Brightness factor = Two's Complement(Integer);

For example, if brightness factor is 3, register value is 8'h03 and if brightness factor is -3, register

value is 8'hfd.

Chrominance Processing Saturation adjustment

For saturation adjustment, Cb,Cr digital Channels are scaled by the saturation factor. Saturation

factor resolution is 1/128 and its range is 0 ~ 255/128.

Edge Enhancement

Edge enhancement is performed for increasing sharpness of image. Edge weight factor is user-

programmable and its range is 0.3 ~ 1.0.

Chroma Suppression

Chroma suppression is performed in the dark environment for suppressing the color and decreasing

dark bad pixel effect. Suppression level is varied in accordance with amplifier gain and saturation level

is user-programmable.

Automatic Flicker Cancellation

Banding noise, caused by difference between frequency of light sources and frequency of integration

time of pixel, is always generated in CMOS image sensor. For Automatic Flicker Cancellation,

integration time is adjusted automatically in accordance with frequency of light sources.

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Output Formatting

The output formats such as YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, RGB 5:6:5 and Bayer Raw Data

are supported. Possible output bus widths are 8 bits and 16bits, and the sequence of Cb and Cr or R

and B are programmable. The output formats are compatible with Recommendation CCIR-601, CCIR-

656.

Auto Exposure Control

Y mean value is continuously calculated every frame, and the integration time or amp gain value are

increased or decreased according to difference between target Y mean value and current frame Y

mean value.

Auto White Balance

Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values'

displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.

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Addres

Default

Symbol

(Hex)

Description

DEVID

Device ID

SCTRA

Sensor Control A

SCTRB

Sensor Control B

SCTRC

Sensor Control C

RSAU

Row Start Address Upper

RSAL

Row Start Address Lower

CSAU

Column Start Address Upper

CSAL

Column Start Address Lower

WIHU

Window Height Upper

WIHL

Window Height Lower

WIWU

Window Width Upper

WIWL

Window Width Lower

HBLU

Horizontal Blank Time Upper

HBLL

Horizontal Blank Time Lower

VBLU

Vertical Blank Time Upper

VBLL

Vertical Blank Time Lower

RGAIN

Red Color Gain

GGAIN

Green Color Gain

BGAIN

Blue Color Gain

AMPGAIN

Amp Gain for Pixel Output

AMPMIN

Amp Gain Minimum Value

AMPMAX

Amp Gain Maximum Value

AMPNOM

Amp Gain Normal Value

AMPBIAS

CDS Bias , Amplifier Bias

RSTCLMP

Reset Level Clamp Enable, Reset Value

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ADCBIAS

ADC Bias Control

OREDI

ADC Initial Offset Value for Optical Black Red

OGRNI

ADC Initial Offset Value for Optical Black Green

OBLUI

ADC Initial Offset Value for Optical Black Blue

BLKTH

Black Level Threshold Value

ISPFUN

Image Signal Processing Functions Enable

OUTFMT

Image Data Output Format

OUTINV

Output Signal Inversion

EDGEWT

Edge Enhancement Weight

CRCM11

Color Correction matrix coefficient 11

CRCM12

Color Correction matrix coefficient 12

CRCM13

Color Correction matrix coefficient 13

CRCM21

Color Correction matrix coefficient 21

CRCM22

Color Correction matrix coefficient 22

CRCM23

Color Correction matrix coefficient 23

CRCM31

Color Correction matrix coefficient 31

CRCM32

Color Correction matrix coefficient 32

CRCM33

Color Correction matrix coefficient 33

GMAP0

Start point for gamma line segment 0

GMAP1

Start point for gamma line segment 1

GMAP2

Start point for gamma line segment 2

GMAP3

Start point for gamma line segment 3

GMAP4

Start point for gamma line segment 4

GMAP5

Start point for gamma line segment 5

GMAP6

Start point for gamma line segment 6

GMAP7

Start point for gamma line segment 7

GMAP8

Start point for gamma line segment 8

GMAP9

Start point for gamma line segment 9

GMAS0

Slope value for gamma line segment 0

GMAS1

Slope value for gamma line segment 1

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GMAS2

Slope value for gamma line segment 2

GMAS3

Slope value for gamma line segment 3

GMAS4

Slope value for gamma line segment 4

GMAS5

Slope value for gamma line segment 5

GMAS6

Slope value for gamma line segment 6

GMAS7

Slope value for gamma line segment 7

GMAS8

Slope value for gamma line segment 8

GMAS9

Slope value for gamma line segment 9

BRIGHTY

Brightness factor for brightness adjustment

SATCR

Saturation factor for Saturation adjustment

SATCB

Saturation factor for Saturation adjustment

EDTHLO

Edge Enhancement Vth Low

EDTHHI

Edge Enhancement Vth High

CHSUPFNC

Chroma Suppression Function

AEMODE1

Auto Exposure Control Mode 1

AEMODE2

Auto Exposure Control Mode 2

CSCMODE

Color Space Conversion Mode Select

INTH

Integration Time

High

INTM

Integration Time

Middle

INTL

Integration Time

Low

AETRGT

Luminance Target Value

AELFBND

Y frame mean value displacement boundary

AEULBND

Y frame mean value displacement from AE target where AE update
speed transits from 2x integration unit speed to 1x integration unit
speed

ASFCON

AE Speed and Frame Control

AESTEPH

AE Anti-Banding Step High

AESTEPM

AE Anti-Banding Step Middle

AESTEPL

AE Anti-Banding Step Low

AEINTH

AE Integration Time Limit High

AEINTM

AE Integration Time Limit Middle

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AEINTL

AE Integration Time Limit Low

AWBMODE1

Auto White Balance Control Mode 1

AWBMODE2

Auto White Balance Control Mode 2

CBTRGT

Cb Frame Mean Value for AWB.

CRTRGT

Cr Frame Mean Value for AWB.

AWBLBND

Cb, Cr Frame Mean Displacement from Cb Target and Cr Target
where AWB goes into LOCK state

AWBULBND

Displacement from ideal white pixel where AWB release from LOCK
state

AWBWBND

Displacement from ideal white pixel where AWB recognizes a pixel
as a white pixel affected by light source

AESTAT

Current AE Operation Status

AWBSTAT

Current AWB Operation Status

LUMEAN

Active Y Frame Mean Value

CBMEAN

Active Cb Frame Mean Value

CRMEAN

Active Cr Frame Mean Value

BNDGMIN

Minimum gain value with Anti-Banding enabled

BNDGMAX

Maximum gain value with Anti-Banding enabled

AWBWHT

During Cb, Cr frame mean value calculation, AWB discards pixel of
which luminance is larger than this register value.

AWBBLK

During Cb, Cr frame mean value calculation, AWB discards pixel of
which luminance is smaller than this register value.

AWBVALID

AWB update when the number of valid color pixel is larger than (this
minimum value x 64)

DPCMODE

Dark Bad Pixel Concealment Mode selection

DPCINTVALH

Integration Time Value High Byte where filtering operation gets active
when dark bad pixel Concealment mode is enabled.

DPCINTVALM

Integration Time Value Middle Byte where filtering operation gets
active when dark bad pixel Concealment mode is enabled.

DPCINTVALL

Integration Time Value Lower Byte where filtering operation gets
active when dark bad pixel Concealment mode is enabled.

DPCGTH

Neighbor-differential threshold value that specify G dark bad pixel

DPCCTH

Neighbor-differential threshold value that specify R/B dark bad pixel

DPCGAINVAL

Reference of Amp Gain which Dark Bad Pixel Concealment mode is
enabled or disabled

CONTY

Contrast factor for Contrast Adjustment

PCTRA

PLL Control Mode A

PCTRB

PLL Control Mode B

PFDDIVH

PLL Feedback Divisor High

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Device ID [DEVID : 00h : 50h]

Product ID

Revision Number

High Nibble represents Sensor Resolution, Low Nibble represents Revision Number.

Sensor Control A [SCTRA : 01h : 13h]

Reserved

X-Flip

Y-Flip

Video Mode

X-Flip

Image is horizontally flipped

Y-Flip

Image is vertically flipped

111 1/6 scaling QCIF mode

110 1/3 scaling CIF mode

101 5/18 scaling QVGA mode

100 5/9 scaling VGA mode

011 5x5 linear color interpolation mode

010 1/4 sub-sampling mode

001 1/16 sub-sampling mode

Video Mode

000 Bayer output mode

Sensor Control B [SCTRB : 02h : 00h]

AE/AWB

Block

Sleep

Datapath

Block

Sleep

Analog

Block

Sleep

Mode

Strobe

Enable

Clock Division

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AE/AWB Block Sleep AE/AWB block goes into sleep mode with this bit set to high.

Datapath Block Sleep Image processing datapath block goes into sleep mode with this bit set to

high.

Analog Block Sleep

all internal analog block goes into sleep mode with this bit set to high. With

All Digital Block Sleep active, sensor goes into power down mode.

Sleep Mode

all internal digital and analog block goes into sleep with this bit set to high.

Strobe Enable

When strobe signal is enabled by this bit, STROBE pin will indicates when

strobe light should be splashed in the dark environment to get adequate

lighted image.

Clock Division

divides input master clock(IMC) for internal use. Internal divided clock

frequency(DCF) is defined as master clock frequency(MCF) divided by

specified clock divisor. Internal divided clock frequency(DCF) is as follows.

000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8

100 : MCF/16, 101 : MCF/32, 110 : MCF/64, 111 : MCF/128

Sensor Control C [SCTRC : 03h : 01h]

reserved

HSYNC in

VBLANK

Unit

Unified

Gain

Black

Level Data

Enable

Black

Level

Compens-

ation

HSYNC in VBLANK

0 : There are no valid HSYNC during valid VBLANK.

1 : There are valid HSYNC during valid VBLANK. At time, VBLANK unit must be Line unit.

VBLANK

HSYNC

VBLANK unit

0 : Line unit. VBLANK unit is based on multiple line period time of sensor.

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1 : Pixel unit. VBLANK unit is based on multiple pixel clock period time of sensor.

Unified Gain

1 : G analog gain is used for R,G and B analog gain.

0 : R,G and B analog gain is used

individually.

Black Level Data Enable

HSYNC is generated for light-shielded pixels in 4 lines.

Black Level Compensation

Black level average values of light-shielded pixels are compensated when active image data is

produced.

Row Start Address Upper [RSAU : 08h : 00h]

Reserved

Row Start Address

Upper

Row Start Address Lower [RSAL : 09h : 02h]

Row Start Address Lower

Row Start Address register defines the row start address of image read out operation.

Column Start Address Upper [CSAU : 0ah : 00h]

Reserved

Column Start Address Upper

Column Start Address Lower [CSAL : 0bh : 02h]

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Column Start Address Lower

Column Start Address register defines the column start address of image read out operation.

Window Height Upper [WIHU : 0ch : 03h]

Reserved

Window Height Upper

Window Height Lower [WIHL : 0dh : 60h]

Window Height Lower

Window Height register defines the height of image to be read out.

Window Width Upper [WIWU : 0eh : 04h]

Reserved

Window Width Upper

Window Width Lower [WIWL : 0fh : 80h]

Window Width Lower

Window Width Address register defines the width of image to be read out.

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Horizontal Blank Time Upper [HBLU : 10h : 00h]

Horizontal Blank Time Upper

Horizontal Blank Time Lower [HBLL : 11h : d0h]

Horizontal Blank Time Lower

HBLANK Time register defines data blank time between current line and next line by using Sensor

Clock Period unit, and should be larger than 208(d0h).

Vertical Blank Time Upper [VBLU : 12h : 00h]

Vertical Blank Time Upper

Vertical Blank Time Lower [VBLL : 13h : 08h]

Vertical Blank Time Lower

VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates

frame boundary between continuous frames.

Each sensor has a little different photo-diode characteristics so that the sensor provides internal

adjustment registers that calibrates internal sensing circuit in order to get optimal performance.

Sensor characteristics adjustment registers are as below.

Red Color Gain [RGAIN : 14h : 08h]

Reserved

Red Amplifier Gain

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Green Color Gain [GGAIN : 15h : 08h]

Reserved

Green Amplifier Gain

Blue Color Gain [BGAIN : 16h : 08h]

Reserved

Blue Amplifier Gain

There are three color gain registers for R, G, B pixels, respectively. Programmable range is from 0.5X
~ 2.5X. Effective Gain = 0.5 + B<4:0>/16. These registers may be used for white balance and color
effect with independent R,G,B color control. Default gain is 1X.

Amp Gain [AMPGAIN : 17h : 08h]

Reserved

Amp Gain

Amp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable
range is from 0.5X ~ 8.5X. Default gain is 1X.
Gain = 0.5 + B<6:0>/16

Amp Gain Minimum Value [AMPMIN : 18h : 10h]

Reserved

Amp Gain Minimum

Amp Gain Minimum Value is minimum value of amplifier gain when sensor adjusts amplifier gain for

auto exposure control. Programmable range is same as Amp Gain. Recommended value is 1.5X.

Amp Gain Maximum Value [AMPMAX : 19h : 28h]

Reserved

Amp Gain Maximum

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Amp Gain Maximum Value is maximum value of amplifier gain when sensor adjusts amplifier gain for

auto exposure control. Programmable range is same as Amp Gain. Recommended value is 3X.

Amp Gain Normal Value [AMPNOM : 1ah : 18h]

Reserved

Amp Gain Normal

Amp Gain Normal Value is reference value of amp gain when sensor adjusts amp gain for auto

exposure control. First, sensor controls integration time before adjusting amp gain for auto exposure

control. After integration time is changed to the minimum or maximum value, sensor adjusts amp gain

from this register value. Refer to figure of AE mode1 register(60H).

Programmable range is same as amp gain. Recommended value is 2X.

ASP Bias [ASPBIAS : 1bh : 13h]

Reserved

Pixel Bias

Amplifier Bias

Pixel Bias

controls the amount of current in internal pixel bias circuit to amplify pixel output

effectively. The larger register value increases the amount of current.

Amplifier Bias

controls the amount of current in internal amplifier bias circuit to amplify pixel

output effectively. The larger register value increases the amount of current.

Reset Level Clamp [RSTCLMP : 1ch : 07h]

Reserved

Clamp On

Reset Level Clamp

Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is

captured as black image in image sensor regardless of correlated double sampling. To solve this

extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp

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controls the reset data voltage to prevent inversion of extremely bright image. The larger register value

clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at

appropriate voltage level.

ADC Bias [ADCBIAS : 20h : 02h]

Reserved

ADC Bias

ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively.

ADC Initial Offset Value for Optical Black Red [OREDI : 21h : 7fh]

Red Pixel Black Offset

ADC Initial Offset Value for Optical Black Green [OGRNI : 22h : 7fh]

Green Pixel Black Offset

ADC Initial Offse t Value for Optical Black Blue [OBLUI : 23h : 7fh]

Blue Pixel Black Offset

These registers control the offset voltage of ADC that changes the black level value for light-shielded

pixels, R,G,B respectively. Register bit functions are composed as follows.

Pixel Black Offset[7]

The bit specifies whether to subtract or add offset voltage in ADC input for

light-shielded pixels.

Pixel Black Offset[6:0] This value specifies the amount of offset voltage for light-shielded pixels.

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ISP Function Enable [ISPFUN : 30h : ffh]

Reserved

Contrast

Adjustment

Chroma

Suppression

Edge

Enhancement

Color Space

Conversion

Color

Correction

Color

Interpolation

Gamma

Correction

Contrast Adjustment

0 : Disable.

1 : Enable. Y Output multiplied by Contrast factor

Chroma Suppression

0 : Disable.

1 : Enable. Chroma Suppressed Cb,Cr Output

Edge Enhancement

0 : Disable.

1 : Enable.

Color Space Conversion

0 : Disable. R,G,B Output

1 : Enable. Y,Cb,Cr Output

Color Correction

0 : Disable.

1 : Enable.

Color Interpolation

0 : Disable.

1 : Enable.

Gamma Correction

0 : Disable. Normal Bayer Output

1 : Enable. Gamma Corrected Bayer Output

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Output Format [OUTFMT : 31h : 31h]

Gamma-

Corrected

Bayer

Bayer 8bit

Output

Cb/B First

Y First

YCbCr

4:4:4 / 4:2:2

RGB

4:4:4

RGB 565

8 bit Output

Gamma-Corrected

Bayer

Gamma-corrected Bayer data are output when Bayer mode is set in SCTRA

Bayer 8bit Output

Bayer data is output with 8bit mode, two LSB of 11 bit Bayer data is stripped

out.

Cb/B First

Cb(B) pixel in front of Cr(R) pixel in 16bit or 8bit video data output modes.

Y First

Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is

meaningful only with YCbCr 4:2:2 8bit output mode.

YCbCr

4:4:4 / 4:2:2

This bit is high, output format is YCbCr 4:4:4 16bit mode, otherwise output

format is YCbCr 4:2:2 8bit/16bit mode.

RGB 4:4:4

R,G,B 24bit data for a pixel is produced with 16bit output mode.

RGB 565

Data format of RGB 565 mode is composed with {R[7:3]/G[7:5]} ,

{G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. OUTFMT[5](Cb/B First)

8 Bit Output

Image Data is produced only in Y[7:0]. C[7:0] should be discarded.

Default mode of Output Format is YCbCr 4:2:2 8bit mode.

Output Signal Inversion [OUTINV : 32h : 00h]

Reserved

Clocked

HSYNC

VSYNC

inversion

HSYNC

inversion

VCLK

inversion

Clocked HSYNC

In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate

during normal HSYNC time

VSYNC inversion

VSYNC output polarity is inverted

HSYNC inversion

HSYNC output polarity is inverted

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VCLK inversion

VCLK output polarity is inverted

Edge Enhancement Weight [EDGEWT : 33h : 02h]

Reserved

Edge Enhancement Weight

Edge Enhancement Weight range is 0.3(3'h000) ~ 1(3'h111), and default value is 0.5(3'h010). As

Edge Enhancement Weight is large, the effect of Edge Enhancement grows stronger.

Color Correction Matrix Coefficient 11 [CRCM11 : 34h : 4ch]

Color Correction Matrix Coefficient 11

Color Correction Matrix Coefficient 12 [CRCM 12 : 35h : ech]

Color Correction Matrix Coefficient 12

Color Correction Matrix Coefficient 13 [CRCM 13 : 36h : 08h]

Color Correction Matrix Coefficient 13

Color Correction Matrix Coefficient 21 [CRCM 21 : 37h : f0h]

Color Correction Matrix Coefficient 21

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Color Correction Matrix Coefficient 22 [CRCM 22 : 38h : 76h]

Color Correction Matrix Coefficient 22

Color Correction Matrix Coefficient 23 [CRCM 23 : 39h : dbh]

Color Correction Matrix Coefficient 23

Color Correction Matrix Coefficient 31 [CRCM 31 : 3ah : feh]

Color Correction Matrix Coefficient 31

Color Correction Matrix Coefficient 32 [CRCM 32 : 3bh : e8h]

Color Correction Matrix Coefficient 32

Color Correction Matrix Coefficient 33 [CRCM 33 : 3ch : 5ah]

Color Correction Matrix Coefficient 33

Gamma Segment Start Points

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Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma

approximation. Current default gamma curve is very selected for optimum gray gradation.

Gamma Point 0 [GAMP0 : 40h : 00h]

Gamma Point 0

Gamma Point 1 [GMAP1 : 41h : 04h]

Gamma Point 1

Gamma Point 2 [GMAP2 : 42h : 1ch]

Gamma Point 2

Gamma Point 3 [GMAP3 : 43h : 34h]

Gamma Point 3

Gamma Point 4 [GMAP4 : 44h : 54h]

Gamma Point 4

Gamma Point 5 [GMAP5 : 45h : 78h]

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Gamma Slope 1 [GMAS1 : 51h : 80h]

Gamma Slope 1

Gamma Slope 2 [GMAS2 : 52h : 60h]

Gamma Slope 2

Gamma Slope 3 [GMAS3 : 53h : 40h]

Gamma Slope 3

Gamma Slope 4 [GMAS4 : 54h : 24h]

Gamma Slope 4

Gamma Slope 5 [GMAS5 : 55h : 18h]

Gamma Slope 5

Gamma Slope 6 [GMAS6 : 56h : 14h]

Gamma Slope 6

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Gamma Slope 7 [GMAS7 : 57h : 0fh]

Gamma Slope 7

Gamma Slope 8 [GMAS8 : 58h : 05h]

Gamma Slope 8

Gamma Slope 9 [GMAS9 : 59h : 02h]

Gamma Slope 9

Brightness Factor Y [BRIGHTY : 5ah : 00h]

Brightness Factor Y

Brightness Adjustment is performed for summing Y data and Brightness Factor Y. Brightness Factor

Y is two's complement and its range is 128 ~ 127.

Bright Y = Y data + Brightness Factor Y.

for positive values, B<7:0> = Integer;

for negative values, B<7:0> = Two's Complement(Integer);

Saturation Factor Cr [SATCR : 5bh : 80h]

Saturation Factor Cr

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Saturation Factor Cb [SATCB : 5ch : 80h]

Saturation Factor Cb

Saturation Adjustment is performed for multiplying Cr,Cb data by Saturation Factor Cr,Cb,

respectively. Programmable range of Saturation Factor Cb,Cr is 0 ~ 2.

For instant, Sat Cb = Cb data * B<7:0>/128.

Edge Enhancement Threshold Low [EDTHLO : 5dh : 05h]

Edge Enhancement Threshold Low

Edge Enhancement Threshold High [EDTHHI : 5eh : 80h]

Edge Enhancement Threshold High

Chroma Suppression Function [CHSUPFNC : 5fh : 64h]

Saturation Level

Suppression Gain Minimum

11 0% of difference between Current Cb,Cr data and reference Cb,Cr level. So,

Chroma Suppressed Cb,Cr data are equal to Current Cb,Cr data.

10 25% of difference between Current Cb,Cr data and reference Cb,Cr level.

01 50% of difference between Current Cb,Cr data and reference Cb,Cr level.

Saturation Level

00 75% of difference between Current Cb,Cr data and reference Cb,Cr level.

Suppression Gain

Minimum

When Amp Gain is greater than Suppression Gain Minimum, Chroma

Suppression Function is started.

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Anti-Banding Enable

When Anti-Banding is enabled, AE initializes Integration Time registers[63h-

65h] to 4 x Anti-Banding Step value[6ah-6ch], and integration

increment/decrement amount is set to Anti-Banding Step value in order to

remove banding noise caused by intrinsic energy waveform of light sources.

Banding noise is inherent in CMOS image sensor that adopts rolling shutter

scheme for image acquisition. In this mode, AE operates with very large unit,

typically a reciprocal of (2 x power line frequency), so that minute integration

time tuning is not liable. Therefore, this mode is recommended for only indoor

use.

Full Window

With this bit set to high, window mode is discarded and full image data is

accounted for AE Y frame mean evaluation

1/8 center weighted window mode. Weighting ratio is 8:1 for inside

area vs. outside area

1/8 center only window mode.

1/4 center weighted window mode. Weighting ratio is 4:1 for inside

area vs. outside area

Window Mode

1/4 center only window mode.

AE Speed

(fast)11 10 01 00(slow)

Gain-Only control mode. Only preamp gain is controlled to get

optimum exposure state.

Time-Only control mode. Only integration time is controlled to get

optimum exposure state.

Time-Gain control mode. Integration time and preamp gain are

controlled to get optimum exposure state.

AE Mode

AE function is disabled

AE Mode Control 2 [AEMODE2 : 61h : 5dh]

Reserved

Gain Speed

Integration

Time Fine

Tune

Amp

Gain Fine

Tune

Anti-

Banding

Minimum

Break

AE Sub-

sampling

mode

AE Analog

Gain

Control

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Gain Speed

Gain update speed is specified as follows.

(fast)11 10 01 00(slow)

Integration Time Fine

Tune

Integration time fine tuning is performed when AE arrive around AE Fine Tune

Boundary to settle into AE lock state smoothly.

Amp Gain Fine Tune

Amp gain fine tuning is performed when AE arrive around AE Fine Tune

Boundary to settle into AE lock state smoothly.

Anti-Banding Minimum

Break

When AE is still of out lock state despite that AE preamp analog gain update

value exceeds preamp minimum gain value(18h) and integration time(63h-

65h) is reached to AE Anti-Banding Step(6ah-6ch), integration time(63h-65h)

is broken to less than AE Anti-Banding Step(6ah-6ch).

AE Sub-sampling

Mode

AE statistics is executed on 1/4 of original image data to save power

consumption

AE Analog Gain

Control

AE updates Amp gain register(17h) in order to reach optimum exposure state

Color Space Conversion Mode [CSCMODE : 62h : 00h]

Reserved

CSC Mode

Reserved

CSC Mode

0 : Mode 1

1 : Mode 2

Integration Time High [INTH: 63h : 13h]

Integration Time Higher

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Integration Time Middle [INTM: 64h: 88h]

Integration Time Middle

Integration Time Low [INTL: 65h: 00h]

Integration Time Lower

Integration time value register defines the time which active pixel element evaluates photon energy

that is converted to digital data output by internal ADC processing. Integration time is equivalent to

exposure time of general camera so that integration time needs to be increased in dark environment

and decreased according to lighting condition. Maximum integration time is register maximum

value(2

-1) x sensor clock period (52ns, SCF 19.2Mhz) = 0.87sec.

SCF = Sensor Clock Frequency

Luminance Target Value [AETRGT : 66h : 70h]

Luminance Target

This register defines the target luminance value for AE operation.

AE Lock & Fine Tune Boundary [AELFBND : 67h : a2h]

AE Fine Boundary

AE Lock Boundary

AE Lock Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which

AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded,

and instead AE Speed Unlock Boundary is used as Lock boundary.

AE Fine Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which

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AE start to tune fine integration time or amp gain in order to goes into lock state smoothly.

AE Unlock Boundary [AEULBND : 68h : 2ah]

AE Unlock Boundary

AE Speed Boundary 0 specifies Y Frame Mean displacement from AE Target where integration time

increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In

anti-banding mode, this boundary is used as lock boundary for exposure control.

AE Speed and Frame Control [ASFCON : 69h : 00h]

Reserved

AE Speed 2

Y Frame Control

Cb,Cr Frame Control

AE Speed 2

(fast)11 10 01 00(slow)

4 Frame mean Value. ( For AE )

2 Frame mean Value.

Y Frame Control

01, 00 1 Frame mean Value.

4 Frame mean Value. ( For AWB )

2 Frame mean Value.

Cb,Cr Frame Control

01, 00 1 Frame mean Value.

AE Speed 2 is different in use to AE Speed 1. When Y Frame Mean is out of Unlock boundary, AE

updates quickly Amp Gain register(17h) in order to reach Lock boundary state.

Gain update speed is specified as follows.

(fast)11 10 01 00(slow)

Frame Control register can be use 1, 2, 4 Frame mean Value. 4 Frame mean value has a history

component of previous 3 Frame mean Value. To use 1 Frame mean Value is that AE changed every

Frame instantly.

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AE Anti-Banding Step High [AESTEPH : 6ah : 02h]

Reserved

Integration Step Higher

AE Anti-Banding Step Middle [AESTEPM : 6bh : eeh]

Integration Step Middle

AE Anti-Banding Step Low [AESTEPL : 6ch : 00h]

Integration Step Lower

AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled.

Anti-Banding Step value is resolved by the following equation.

Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency)

The default value is set with SCF 19.2Mhz, 50Hz power line, that is,

Anti-Banding Step Value = 19.2Mhz / (2 x 50) = 192000d = 02ee00h

AE Integration Time Limit High [AEINTH : 6dh : 3ah]

AE Integration Time Limit Higher

AE Integration Time Limit Middle [AEINTM : 6eh : 98h]

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Auto White Balance

Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values'

displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.

AWB Unlock Boundary [76h]

Cb/Cr Target [73h-74h]

AWB Lock Boundary [75h]

AWVB White Pixel Boundary [77h]

AWB Lock Boundary [75h]

AWB Unlock Boundary [76h]

AWB White Pixel Boundary [77h]

80h

Cb/Cr Frame Mean

FFh

AWB Mode Control 1 [AWBMODE1 : 70h : 41h]

Reserved

Full

Window

Reserved

Window

Mode

AWB speed

Reserved

AWB On

Full Window

With this bit set to high, window mode is discarded and full image data is

accounted for AE Y frame mean evaluation

1/4 center weighted window mode. Weighting ratio is 4:1 for inside

area vs. outside area

Window Mode

1/4 center only window mode.

AWB Speed

(Fast)11 - 10 - 01 - 00(slow)

AWB On

Auto White Balance Control Enabled

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AWB Mode Control 2 [AEMODE2 : 71h : 02h]

Reserved

AWB Low

Speed

AWB Sub-

sampling

mode

AWB

Analog

Gain

Control

Reserved

AWB Low Speed

With this bit set to high, analog gain speed is decreased to 1/4 of the normal

speed.

AWB Sub-sampling

Mode

AWB statistics is executed on 1/4 of original image data to save power

consumption

AWB Analog Gain

Control

AWB updates R/B gain registers(14h,16h) in order to reach optimum white

balance state

Cb Frame Mean Value [CBTRGT : 73h : 80h]

Cb Frame Mean

This register defines Cb target frame mean value for AWB operation.

Cr Frame Mean Value [CRTRGT : 74h : 80h]

Cr Frame Mean

This register defines Cr target frame mean value for AWB operation.

AWB Lock Boundary [AWBLBND : 75h : 02h]

Reserved

AWB Lock Boundary

It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) value where AWB

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goes into LOCK state.

AWB Unlock Boundary [AWBULBND : 76h : 06h]

AWB Unlock Boundary

It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) where AWB is

released from LOCK state. AWB operation retains LOCK state unless Cb/Cr frame mean values'

displacement value exceeds this boundary. The value should be larger AWB Lock Boundary.

AWB White Pixel Boundary [AWBWBND : 77h : 30h]

AWB White Pixel Boundary

When Cb/Cr frame mean values' displacement from Cb/Cr Target exceeds AWB White Pixel

Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation.

Current AE Operation Status [AESTAT : 7bh : RO]

AE Mode State

AE Lock state

AE Mode State This nibble represents the mode where internal Y plane FSM is currently placed

among time-gain control, time-only control, or gain-only control modes.

AE Lock State Y channel FSM status, "0000" means that AE Y plane is in lock state

Current AWB Operation Status [AWBSTAT : 7ch : RO]

reserved

AE/AWB

Lock

Cb Lock State

Cr Lock State

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AE/AWB Lock This single status bit indicates that AE and AWB are in lock state for optimum still

image capture.

Cb Lock State

Cb channel FSM status. "00" means that AWB Cb plane is in lock state

Cr Lock State

Cr channel FSM status. "00" means that AWB Cr plane is in lock state

Active Y Frame Mean Value [LUMEAN : 7dh : RO]

Y Frame Mean

The register reports current Y plane frame mean value.

Active Cb Frame Mean Value [CBMEAN : 7eh : RO]

Cb Frame Mean

The register reports current Cb plane frame mean value.

Active Cr Frame Mean Value [CRMEAN : 7fh : RO]

Cr Frame Mean

The register reports current Cr plane frame mean value.

Minimum Anti-Banding Gain [BNDGMIN : 80h : 08h]

Minimum Anti-Banding Gain

The register specifies the minimum limit to which AE may decrease preamp gain or Y digital gain in

order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition

is met.

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Maximum Anti-Banding Gain [BNDGMAX : 81h : 18h]

Maximum Anti-Banding Gain

The register specifies the maximum limit to which AE may increase preamp gain or Y digital gain in

order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition

is met.

AE Lock Boundary < (AE Target - Y Frame Mean) < AE Unlock Boundary.

AWB Luminance Higher Limit [AWBWHT : 8ah : c8h]

AWB Luminance Higher Limit

During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is larger

than this register value.

AWB Luminance Lower Limit [AWBBLK : 8bh : 0ah]

AWB Luminance Lower Limit

During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is smaller

than this register value.

AWB Valid Number of Pixel [AWBVALID : 8ch : 02h]

AWB Valid Number of Pixel

AWB update when the number of valid color pixel is larger than (this valid value x 64).

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Dark Bad Pixel Concealment Mode [DPCMODE : 90h : 01h]

Reserved

Dark Bad Pixel

Concealment Mode

Dark Bad Pixel Concealment is always performed.

Dark Bad Pixel Concealment is performed when

Integration Time (63h-65h) exceeds Dark Bad Integration

Time(91h-93h)

Dark Bad Pixel Concealment

Mode

11, 00

Dark Bad Pixel Concealment is turned off

Dark Bad Integration Time High [DPCINTH : 91h : 29h]

Dark Integration Time Higher

Dark Bad Integration Time Middle [DPCINTM : 92h : dah]

Dark Integration Time Middle

Dark Bad Integration Time Low [DPCINTL : 93h : 49h]

Dark Integration Time Lower

Dark Bad Integration Time registers(91h-93h) specify minimum integration time value(63h-65h) where

dark bad concealment operation is performed when dark bad pixel concealment mode is "01 (binary)".

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Dark G Threshold [DPCGTH : 94h : 20h]

Dark G Threshold

The register value specify the current G pixel's differential value with neighboring G pixels, and is used

to check whether current G pixel is dark bad pixel or not.

Dark R/B Threshold [DPCGTH : 95h : 20h]

Dark R/B Threshold

The register value specify the current R or B pixel's differential value with neighboring G pixels, and is

used to check whether current R or B pixel is dark bad pixel or not.

Reference of Amp Gain for Dark Bad Pixel Concealment [DPCGAIN : 96h : 38h]

Reference of Amp Gain for Dark Bad Pixel Concealment

Amp Gain exceeds Reference of Amp Gain for Dark Bad Pixel Concealment, dark bad concealment

operation is performed when dark bad pixel concealment mode is "01

Contrast factor Y [CONTY : 97h : 80h]

Contrast factor Y

Contrast Adjustment is performed for multiplying Y data by Contrast Factor Y, respectively.

Programmable range of Contrast Factor Y is 0 ~ 2.

Cont Y = Y data * B<7:0>/128.

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PLL Control Mode A [PCTRA : a0h : 01h]

Reserved

VCO

Power

Down

PLL

Power

Down

Bypass

Mode

VCO Power Down

(Active High)

When VCO Power Down is active, VCO does not oscillate. For getting out of

VCO Power Down, VCO initialization is required.

PLL Power Down

(Active High)

When PLL Power Down is active, digital circuits of PLL do not operate and the

charge pump circuits is disabled. Also Bypass Mode or Sleep

Mode(SCTRB[4]) register is set to high, PLL goes into sleep.

PLL output clock is 1/F(ck).

Bypass Mode

PLL output clock is the same of PLL input clock.

* VCO initialization

To ensure the proper operation of the PLL, the activation of VCO initialization signal is required just

after the deactivation of the VCO Power Down. During power-up sequence VCO initialization signal is

recommended for more than 100ns.

PLL Control Mode B [PCTRB : a1h : 1dh]

Reserved

Post Divisor

Charge Pump Bias

The value of Post Divisor according to the output frequency

F(ck)

Post Divisor

Min

Max

5MHz

12.5MHz

10MHz

25MHz

20MHz

50MHz

40MHz

100MHz

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PLL Feedback Divisor High [PFDDIVH : a4h : 00h]

PLL Feedback Divisor High

PLL Feedback Divisor Low [PFDDIVL : a5h : 02h]

PLL Feedback Divisor Low

The operation frequency of PLL is related to the proportion of Reference(PREFDIV) to

Feedback(PFDDIV) Divisor. F(ck) is actually determined by the following equation.

)

(

)

(

)

(

)

(

Divisor

eference

Divisor

Feedback

ref

F(ck) : frequency of output

F(ref) : frequency of PLL input

Feedback Divisor : PFDDIV[13:0] + 2

Reference Divisor : 2

Pixel Number High [PXNUMH : b9h : 04h]

Pixel Number High

Pixel Number Low [PXNUML : bah : 00]

Pixel Number Low

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Stable Range variation [STTHVAL : bbh : 30h]

Stable Range variation

Frequency Change Variation [CHTHVAL : bch : 20h]

Frequency Change Variation

AFC Mode Control [AFCMODE : bdh : 00h]

Reserved

AFC Mode

Reserved

AFC

Enable

selected first AFC algorithm

AFC Mode

selected second AFC algorithm

AFC off

AFC Enable

AFC on

50Hz Integration Time High [INTEG50H : c0h : 02h]

50Hz Integration Time High

50Hz Integration Time Middle [INTEG50M : c1h : eeh]

50Hz Integration Time Middle

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Anti-Banding Configuration

For Anti-Banding mode to work correctly, the following registers should be configured to the

appropriate values.

AE Mode

60h

Anti-Banding Enable[7]

AE Anti-Banding Step

6a-6ch

(Sensor Clock Frequency) / (2 x power line frequency)

AE Integration Time Limit

6d-6fh

The value should be multiples of AE Anti-Banding Step

When Anti-Banding is enabled, AE initializes Integration Time registers[63-65h] to 4 x Anti-Banding

Step value[6a-6ch], and integration increment/decrement amount is set to Anti-Banding Step value in

order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding

noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition.

Frame Timing

For clear description of frame timing, clocks' acronyms are reminded in here again.

< Clock Acronym Definition >

MCF : Master Clock Frequency

PCF : PLL Out Clock Frequency

DCF : Divided Clock Frequency

SCF : Sensor Clock Frequency

ICF : Image Processing Clock Frequency

LCF : Line Clock Frequency

VCF : Video Clock Frequency

< Frame Time Calculation >

Core Frame Time is

(IDLE SLOT + Video Height * LCP)

and Real Frame Time is resolved as follows.

When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP),

otherwise is (Core Frame Time + VBLANK * LCP).

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1. 5x5 Color Interpolation Timing (Full Size Mode)

5x5 Color Interpolation Frame Timing Related Parameters

Master Clock Frequency(MCF)

19.2Mhz

PLL Out Clock Frequency(PCF)

MCF*2 = 38.4Mhz

Divided Clock Frequency(DCF)

PCF/1 = 38.4Mhz

Sensor Clock Frequency(SCF)

DCF/2 = 19.2Mhz

Sensor Clock Period(SCP)

1/19.2Mhz = 52ns

Window Width

1152

Window Height

864

HBLANK Value

208

VBLANK Value

VSYNC Mode

Line Mode

Line Clock Period(LCP)

1366 SCPs

Output Bus Width

8bit

VGA Video Output Frequency

SCF * 2 = 38.4Mhz

Final Video Output Size

1152x864

LCP(1366 SCPs)

ISP Dummy

(6 SCPs)

HSYNC (1152 SCPs)

Active Data: 1152 EA

IDLE SLOT(4LCPs + (1024+HBLANK)*4)

HBLANK

(208 SCPs)

VBLANK[VSYNC]

(8 LCPs)

HOLD SLOT

(Integration Time Core Frame Time)

Real Frame

Time

Core Frame

Time

Video Lines is

active every

LCP, that is,

864 Video Lines

for 864 LCPs

If Integration Time < Core Frame Time, Real Frame Time is

4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *

(208+1024)= 1201544 SCPs = 0.062580sec -> 15.979 frame per sec.

else Real Frame Time is

Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger than core frame time.

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 62 -

2003 Hynix Semiconductor Inc.

2. 5x5 Color Interpolation Timing (1/4 Sub-Sampling Mode)

5x5 Color Interpolation Frame Timing Related Parameters

Master Clock Frequency(MCF)

19.2Mhz

PLL Out Clock Frequency(PCF)

MCF*2 = 38.4Mhz

Divided Clock Frequency(DCF)

PCF/1 = 38.4Mhz

Sensor Clock Frequency(SCF)

DCF/2 = 19.2Mhz

Sensor Clock Period(SCP)

1/19.2Mhz = 52ns

Window Width

576

Window Height

432

HBLANK Value

208

VBLANK Value

VSYNC Mode

Line Mode

Line Clock Period(LCP)

1366 SCPs

Output Bus Width

8bit

VGA Video Output Frequency

SCF = 19.2Mhz

Final Video Output Size

576x432

LCP(1366 SCPs)

ISP Dummy

(6 SCPs)

HSYNC (1152 SCPs)

Active Data: 576 EA

IDLE SLOT(4LCPs + (1024+HBLANK)*4)

HBLANK

(208 SCPs)

VBLANK[VSYNC]

(8 LCPs)

HOLD SLOT

(Integration Time Core Frame Time)

Real Frame

Time

Core Frame

Time

Video Lines is

active every

LCP, that is,

432 Video Lines

for 432 LCPs

If Integration Time < Core Frame Time, Real Frame Time is

4 * (208 + 1152+6) SCPs + 432 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *

(208+1024)= 611432 SCPs = 0.031845sec -> 31.402 frame per sec.

else Real Frame Time is

Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger than core frame time.

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 63 -

2003 Hynix Semiconductor Inc.

3. 5x5 Color Interpolation Timing (1/16 Mode)

5x5 Color Interpolation Frame Timing Related Parameters

Master Clock Frequency(MCF)

19.2Mhz

PLL Out Clock Frequency(PCF)

MCF*2 = 38.4Mhz

Divided Clock Frequency(DCF)

PCF/1 = 38.4Mhz

Sensor Clock Frequency(SCF)

DCF/2 = 19.2Mhz

Sensor Clock Period(SCP)

1/19.2Mhz = 52ns

Window Width

288

Window Height

216

HBLANK Value

208

VBLANK Value

VSYNC Mode

Line Mode

Line Clock Period(LCP)

1366 SCPs

Output Bus Width

8bit

VGA Video Output Frequency

SCF/2 = 9.6Mhz

Final Video Output Size

288x216

LCP(1366 SCPs)

ISP Dummy

(6 SCPs)

HSYNC (1152 SCPs)

Active Data: 288 EA

IDLE SLOT(4LCPs + (1024+HBLANK)*4)

HBLANK

(208 SCPs)

VBLANK[VSYNC]

(8 LCPs)

HOLD SLOT

(Integration Time Core Frame Time)

Real Frame

Time

Core Frame

Time

Video Lines is

active every

LCP, that is,

216 Video Lines

for 216 LCPs

If Integration Time < Core Frame Time, Real Frame Time is

4 * (208 + 1152+6) SCPs + 216 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *

(208+1024)= 316376 SCPs = 0.016478sec -> 60.687frame per sec.

else Real Frame Time is

Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger than core frame time.

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 64 -

2003 Hynix Semiconductor Inc.

4. 5x5 Color Interpolation Timing (VgaMode)

5x5 Color Interpolation Frame Timing Related Parameters

Master Clock Frequency(MCF)

19.2Mhz

PLL Out Clock Frequency(PCF)

MCF*2 = 38.4Mhz

Divided Clock Frequency(DCF)

PCF/1 = 38.4Mhz

Sensor Clock Frequency(SCF)

DCF/2 = 19.2Mhz

Sensor Clock Period(SCP)

1/19.2Mhz = 52ns

Window Width

640

Window Height

480

HBLANK Value

208

VBLANK Value

VSYNC Mode

Line Mode

Line Clock Period(LCP)

1366 SCPs

Output Bus Width

8bit

VGA Video Output Frequency

Irregular clock

Final Video Output Size

640x480

LCP(1366 SCPs)

ISP Dummy

(6 SCPs)

HSYNC (1152 SCPs)

Active Data: 640 EA

IDLE SLOT(4LCPs + (1024+HBLANK)*4)

HBLANK

(208 SCPs)

VBLANK[VSYNC]

(8 LCPs)

HOLD SLOT

(Integration Time Core Frame Time)

Real Frame

Time

Core Frame

Time

Video Lines is

active every

LCP, that is,

480 Video Lines

for 864 LCPs

If Integration Time < Core Frame Time, Real Frame Time is

4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *

(208+1024)= 1201544 SCPs = 0.062580sec -> 15.979 frame per sec.

else Real Frame Time is

Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger than core frame time.

VgaMode Frame rate is same as Full Size Mode. And QVgaMode has same frame rate.

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 65 -

2003 Hynix Semiconductor Inc.

5. 5x5 Color Interpolation Timing (CifMode)

5x5 Color Interpolation Frame Timing Related Parameters

Master Clock Frequency(MCF)

19.2Mhz

PLL Out Clock Frequency(PCF)

MCF*2 = 38.4Mhz

Divided Clock Frequency(DCF)

PCF/1 = 38.4Mhz

Sensor Clock Frequency(SCF)

DCF/2 = 19.2Mhz

Sensor Clock Period(SCP)

1/19.2Mhz = 52ns

Window Width

352

Window Height

288

HBLANK Value

208

VBLANK Value

VSYNC Mode

Line Mode

Line Clock Period(LCP)

1366 SCPs

Output Bus Width

8bit

VGA Video Output Frequency

Irregular clock

Final Video Output Size

352x288

LCP(1366 SCPs)

ISP Dummy

(6 SCPs)

HSYNC (1152 SCPs)

Active Data: 352 EA

IDLE SLOT(4LCPs + (1024+HBLANK)*4)

HBLANK

(208 SCPs)

VBLANK[VSYNC]

(8 LCPs)

HOLD SLOT

(Integration Time Core Frame Time)

Real Frame

Time

Core Frame

Time

Video Lines is

active every

LCP, that is,

288 Video Lines

for 864 LCPs

If Integration Time < Core Frame Time, Real Frame Time is

4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *

(208+1024)= 1201544 SCPs = 0.062580sec -> 15.979 frame per sec.

else Real Frame Time is

Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger than core frame time.

QCifMode Frame rate is same as CifMode Frame rate.

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 66 -

2003 Hynix Semiconductor Inc.

Output Data according to Video Mode

Output Data according to Video Mode is controlled by configuring Sensor Control A[01h] and Output

Format register[31h]. Configurable options are specified again for your reference.

Sensor Control A [SCTRA : 01h : 13h]

Reserved

X-Flip

Y-Flip

Video Mode

Output Format [OUTFMT : 31h : 31h]

Gamma-

Corrected

Bayer

Bayer 8bit

Output

Cb/B First

Y First

YCbCr

4:4:4 / 4:2:2

RGB

4:4:4

RGB 565

8 bit Output

Output timings for general configurations are described below. Slot named as "X" means that it is has

no meaningful value and should be discarded. 8bit Output is active, C[7:0] are always Hi-Z state. In

Case of Cb or Cr data, the digit stands for its sequence, respectively. For example, Cb01 is equal to

average of Cb0 and Cb1.

5X5 Mode or Sub-sampling(1/4, 1/16) Mode

1. YCbCr 4:2:2 with 8bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 8bit Output, Y First, Cb/B First

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 68 -

2003 Hynix Semiconductor Inc.

2. YCbCr 4:2:2 with 16bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 16bit Output, Cb/B First

HSYNC

MCLK

1/4 Sub-sampling Video Clock & Output Data

5X5 Mode Video Clock & Output Data

Cr46

Cb46

Cr02

Cb02

Cr46

Cb46

Cr02

Cb02

Cb67

Cr45

Cb45

Cr23

Cb23

Cr01

Cb01

Cb67

Cr45

Cb45

Cr23

Cb23

Cr01

Cb01

Cr04

Cb04

Cr04

Cb04

CLK

Y[7:0]

C[7:0]

CLK

Y[7:0]

C[7:0]

1/16 Sub-sampling Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 69 -

2003 Hynix Semiconductor Inc.

3. YCbCr 4:4:4 with 16bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 16bit Output, Y First, Cb/B First

HSYNC

MCLK

1/4 Sub-sampling Video Clock & Output Data

5X5 Mode Video Clock & Output Data

CLK

1/16 Sub-sampling Video Clock & Output Data

CLK

Cb6

Cr5

Cb5

Cr4

Cb4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Cb6

Cr5

Cb5

Cr4

Cb4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Y[7:0]

C[7:0]

Cb6

Cr4

Cb4

Cr2

Cb2

Cr0

Cb0

Cb6

Cr4

Cb4

Cr2

Cb2

Cr0

Cb0

Y[7:0]

C[7:0]

Cr4

Cb4

Cr0

Cb0

Cr4

Cb4

Cr0

Cb0

Y[7:0]

C[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 70 -

2003 Hynix Semiconductor Inc.

4. RGB 565 with 8bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 8bit Output, Cb/B First, RGB565

HSYNC

MCLK

RG6

GB5

RG5

GB4

RG4

GB3

RG3

GB2

RG2

BG1

RG1

GB0

RG0

RG6

GB5

RG5

GB4

RG4

GB3

RG3

GB2

RG2

BG1

RG1

GB0

RG0

RG6

GB4

RG4

GB2

RG2

GB0

RG0

RG6

GB4

RG4

GB2

RG2

GB0

RG0

GB4

RG4

GB0

RG0

GB4

RG4

GB0

RG0

1/4 Sub-sampling Video Clock & Output Data

5X5 Mode Video Clock & Output Data

CLK

1/16 Sub-sampling Video Clock & Output Data

CLK

Y[7:0]

{G0[4:2]B0[7:3]}

{R0[7:3]G0[7:5]} {G0[4:2]B0[7:3]}

{R0[7:3]G0[7:5]}

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 71 -

2003 Hynix Semiconductor Inc.

5. RGB 565 with 16bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 16bit Output, Cb/B First, RGB565

HSYNC

MCLK

5X5 Mode Video Clock & Output Data

{R0[7:3]G0[7:5]}

RG6

RG5

RG4

RG3

RG2

RG1

RG0

RG6

RG5

RG4

RG3

RG2

RG1

RG0

CLK

GB6

GB5

GB4

GB3

GB2

GB1

GB0

GB6

GB5

GB4

GB3

GB2

GB1

GB0

Y[7:0]

C[7:0]

{G0[4:2]B0[7:3]}

RG6

RG4

RG2

RG0

RG6

RG4

RG2

RG0

1/4 Sub-sampling Video Clock & Output Data

GB6

GB4

GB2

GB0

GB6

GB4

GB2

GB0

RG4

RG0

RG4

RG0

GB4

GB0

GB4

GB0

CLK

Y[7:0]

C[7:0]

1/16 Sub-sampling Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 72 -

2003 Hynix Semiconductor Inc.

6. RGB 4:4:4 with 16bit output

Sensor Control A : 5x5 Mode or Sub-sampling Mode

Output Format : 16bit Output, Cb/B First, RGB4:4:4

HSYNC

MCLK

1/4 Sub-sampling Video Clock & Output Data

5X5 Mode Video Clock & Output Data

CLK

1/16 Sub-sampling Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

Y[7:0]

C[7:0]

Y[7:0]

C[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 73 -

2003 Hynix Semiconductor Inc.

VGA Mode or QVGA Mode

1. YCbCr 4:2:2 with 8bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 8bit Output, Y First, Cb/B First

2. YCbCr 4:2:2 with 16bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 16bit Output, Cb/B First

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

QVGA Mode Video Clock & Output Data

Cb89

Cr67

Cb67

Y10

Cr45

Cb
45

Cr23

Cb23

Cr01

Cb01

Cb89

Cr67

Cb67

Y10

Cr45

Cb
45

Cr23

Cb23

Cr01

Cb01

Cb89

Cr45

Cb
45

Cr01

Cb01

Cb89

Cr45

Cb
45

Cr01

Cb01

CLK

Y[7:0]

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

QVGA Mode Video Clock & Output Data

CLK

RG9

RG7

RG8

RG10

RG6

RG5

RG4

RG3

RG2

RG1

RG0

RG9

RG7

RG8

RG10

RG6

RG5

RG4

RG3

RG2

RG1

RG0

GB9

GB7

GB8

GB10

GB6

GB5

GB4

GB3

GB2

GB1

GB0

GB9

GB7

GB8

GB10

GB6

GB5

GB4

GB3

GB2

GB1

GB0

Y[7:0]

C[7:0]

Y10

Cr89

Cb89

Cr45

Cb45

Cr01

Cb01

Cr89

Cb89

Cr45

Cb45

Cr01

Cb01

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 74 -

2003 Hynix Semiconductor Inc.

3. YCbCr 4:4:4 with 16bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 16bit Output, Y First, Cb/B First

4. RGB 565 with 8bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 8bit Output, Cb/B First, RGB565

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

QVGA Mode Video Clock & Output Data

CLK

Y10

Cr9

Cb9

Cr8

Cb7

Cr7

Cb8

Cr6

Cb10

Cb6

Cr5

Cb5

Cr4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Cr9

Cb9

Cr8

Cb7

Cr7

Cb8

Cr6

Cb10

Cb6

Cr5

Cb5

Cr4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Y[7:0]

C[7:0]

Y10

Cr8

Cb8

Cr6

Cb10

Cb6

Cr4

Cr2

Cb2

Cr0

Cb0

Cr8

Cb8

Cr6

Cb10

Cb6

Cr4

Cr2

Cb2

Cr0

Cb0

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

QVGA Mode Video Clock & Output Data

CLK

GB8

RG7

GB7

RG8

GB6

RG10

RG6

GB5

RG5

GB3

RG3

GB2

RG2

GB1

RG1

GB0

RG0

GB8

RG7

GB7

RG8

GB6

RG10

RG6

GB5

RG5

GB3

RG3

GB2

RG2

GB1

RG1

GB0

RG0

Y[7:0]

GB8

RG8

GB6

RG10

RG6

GB2

RG2

GB0

RG0

GB8

RG8

GB6

RG10

RG6

GB2

RG2

GB0

RG0

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 75 -

2003 Hynix Semiconductor Inc.

5. RGB 565 with 16bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 16bit Output, Cb/B First, RGB565

6. RGB 4:4:4 with 16bit output

Sensor Control A : VGA Mode or QVGA Mode

Output Format : 16bit Output, Cb/B First, RGB4:4:4

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

QVGA Mode Video Clock & Output Data

CLK

RG9

RG7

RG8

RG10

RG6

RG5

RG4

RG3

RG2

RG1

RG0

RG9

RG7

RG8

RG10

RG6

RG5

RG4

RG3

RG2

RG1

RG0

GB9

GB7

GB8

GB10

GB6

GB5

GB4

GB3

GB2

GB1

GB0

GB9

GB7

GB8

GB10

GB6

GB5

GB4

GB3

GB2

GB1

GB0

Y[7:0]

C[7:0]

RG9

RG8

RG5

RG4

RG1

RG0

RG9

RG8

RG5

RG4

RG1

RG0

GB9

GB8

GB5

GB4

GB1

GB0

GB9

GB8

GB5

GB4

GB1

GB0

HSYNC

MCLK

VGA Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

QVGA Mode Video Clock & Output Data

CLK

G10

B10

Y[7:0]

C[7:0]

G10

B10

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 76 -

2003 Hynix Semiconductor Inc.

CIF Mode or QCIF Mode

1. YCbCr 4:2:2 with 8bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 8bit Output, Y First, Cb/B First

2. YCbCr 4:2:2 with 16bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 16bit Output, Cb/B First

HSYNC

Cb45

Cr23

Cb23

Cr01

Cb01

Cb45

Cr23

Cb23

Cr01

Cb01

MCLK

Cb01

Cr01

Cb01

Cr01

Cb01

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

CLK

Y[7:0]

HSYNC

MCLK

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

CLK

Y[7:0]

C[7:0]

Cb45

Cr23

Cb23

Cr01

Cb01

Cb45

Cr23

Cb23

Cr01

Cb01

Cb45

Cr01

Cb01

Cb45

Cr01

Cb01

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 77 -

2003 Hynix Semiconductor Inc.

3. YCbCr 4:4:4 with 16bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 16bit Output, Y First, Cb/B First

4. RGB 565 with 8bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 8bit Output, Cb/B First, RGB565

HSYNC

MCLK

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

CLK

Y[7:0]

C[7:0]

Cr4

Cb4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Cr4

Cb4

Cr3

Cb3

Cr2

Cb2

Cr1

Cb1

Cr0

Cb0

Cr4

Cb4

Cb1

Cr0

Cb0

Cr4

Cb4

Cb1

Cr0

Cb0

HSYNC

MCLK

GB4

RG4

GB3

RG3

GB2

RG2

GB1

RG1

GB0

RG0

GB4

RG4

GB3

RG3

GB2

RG2

GB1

RG1

GB0

RG0

GB4

RG4

GB1

RG1

GB0

RG0

GB4

RG4

GB1

RG1

GB0

RG0

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

CLK

Y[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 78 -

2003 Hynix Semiconductor Inc.

5. RGB 565 with 16bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 16bit Output, Cb/B First, RGB565

6. RGB 4:4:4 with 16bit output

Sensor Control A : CIF Mode or QCIF Mode

Output Format : 16bit Output, Cb/B First, RGB4:4:4

RG4

RG3

RG2

RG1

RG0

RG4

RG3

RG2

RG1

RG0

RG4

RG1

RG0

RG4

RG1

RG0

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

CLK

Y[7:0]

C[7:0]

GB4

GB3

GB2

GB1

GB0

GB4

GB3

GB2

GB1

GB0

GB4

GB1

GB0

GB4

GB1

GB0

HSYNC

MCLK

HSYNC

MCLK

CIF Mode Video Clock & Output Data

QCIF Mode Video Clock & Output Data

CLK

Y[7:0]

C[7:0]

CLK

Y[7:0]

C[7:0]

HV7151SP

CMOS Image Sensor

Confidential

With Image Signal Processing

- 80 -

2003 Hynix Semiconductor Inc.

I2C Chip Interface

The serial bus interface consists of the SDA(serial data) and SCK(serial clock) pins. HV7151SP

sensor can operate only as a slave. The SCK only controls the serial interface. However, MCLK

should be supplied and RESET should be high signal during controlling the serial interface. The Start

condition is that logic transition (High to Low) on the SDA pin while the SCK pin is at high state. The

Stop condition is that logic transition (Low to High) on the SDA pin while the SCK pin is at high state.

To generate Acknowledge signal, the Sensor drives the SDA low when the SCK pin is at high state.

Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an Acknowledge.

The most significant bit of the byte should always be transmitted first.

Register Write Sequences

One Byte Write

22H

01H

04H

Set "Sensor Control A" register into Window mode

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]

*3. Read: acknowledge from sensor

*4. Drive: 01H [sub-address]

*5. Read: acknowledge from sensor

*6. Drive: 04H [Video Mode : VGA]

*7. Read: acknowledge from sensor

*8. Drive: I2C stop condition

ACK

MSB

LSB

SDA

SCK

START

ACK

STOP

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Multiple Byte Write using Auto Address Increment

22H

0cH

03H

60H

*9 *10

Set "AE Integration Step High/Low" register as 5161H with auto address increment

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]

*3. Read: acknowledge from sensor

*4. Drive: 0cH [sub-address]

*5. Read: acknowledge from sensor

*6. Drive: 03H [Window Height Upper]

*7. Read: acknowledge from sensor

*8. Drive: 60H [Window Height Lower]

*9. Read: acknowledge from sensor

*10. Drive: I2C stop condition

Register Read Sequence

22H

1cH

A S

23H

Data of 07H

A P

*5 *6

*10 *11

Read "Reset Level Clamp" register from HV7151SP

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)]

*3. Read: acknowledge from sensor

*4. Drive: 1cH [sub-address]

*5. Read: acknowledge from sensor

*6. Drive: I

C start condition

*7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)]

*8. Read: acknowledge from sensor

*9. Read: Read "Reset Level Clamp" from sensor

*10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low

and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to

prepare for the read transaction end.

*11. Drive: I2C stop condition

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CMOS Image Sensor

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AC/DC Characteristics

Absolute Maximum Ratings

Symbol

Parameter

Units

Min.

Max.

Viopp

I/O block supply voltage

Volts

-0.3

3.3

Vdpp

Internal digital supply voltage

Volts

-0.3

2.5

Vapp

Analog supply voltage

Volts

-0.3

2.5

Vipp

Input signal voltage

Volts

-0.3

3.3

Top

Operating Temperature

-10

Tst

Storage Temperature

-30

Caution: Stresses exceeding the absolute maximum ratings may induce failure.

DC Operating Conditions

Symbol

Parameter

Units

Min.

Max.

Load[pF]

Notes

Vio

I/O block supply voltage

Volt

2.3

2.8

Internal operation supply voltage

Volt

1.6

2.0

Input voltage logic "1"

Volt

2.3

2.5

6.5

Input voltage logic "0"

Volt

0.8

6.5

Output voltage logic "1"

Volt

2.15

Vio

Output voltage logic "0"

Volt

0.4

Output High Current

-4

Output Low Current

Ambient operating temperature

Celsius

-10

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CMOS Image Sensor

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AC Operating Conditions

Symbol

Parameter

Max Operation Frequency

Units

Notes

MCLK

Main clock frequency

1) PLL off : 38.4

2) PLL on :

)

(

)

(Re

Divisor

Feedback

Divisor

ference

MHz

1,2,3

SCK

C clock frequency

400

KHz

1. MCLK may be divided by internal clock division logic for easy integration with high speed video

codec system.

2. Reference Divider and Feedback Divider is registers a3h and a4h, a5h, respectively.

3. Frame Rate : 15 frames/sec at 38.4Mhz and PLL off , HBLANK = 208, VBLANK = 8

4. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface

section

Output AC Characteristics

All output timing delays are measured with output load 60[pF]. Output delay includes the internal

clock path delay and output driving delay that changes in respect to the output load, the operating

environment, and a board design. Due to the variable valid time delay of the output, video output

signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the

stable data transfer between the image sensor and video codec.

Y/C[7:0]

V C L K

Data 0

Data 1

Data 2

HSYNC

Data 3

3ns

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CMOS Image Sensor

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I2C Bus Timing

S D A

S C K

s t o p

s t a r t

t b u f

t l o w

t h d ; s t a

t h d ; d a t

t h i g h

t s u ; d a t

t s u ; s t a

t s u ; s t o

s t o p

s t a r t

t h d ; s t a

Parameter

Symbol

Min.

Max.

Unit

SCK clock frequency

sck

400

KHz

Time that I

C bus must be free before a

new transmission can start

buf

1.2

Hold time for a START

1.0

LOW period of SCK

low

1.2

HIGH period of SCK

high

1.0

Setup time for START

1.2

Data hold time

0.1

Data setup time

250

Rise time of both SDA and SCK

250

Fall time of both SDA and SCK

300

Setup time for STOP

1.2

Capacitive load of SCK/SDA

Part Number HV7151SP