2SK2570
2
Absolute Maximum Ratings (Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
V
DSS
20
V
Gate to source voltage
V
GSS
±
10
V
Drain current
I
D
0.2
A
Drain peak current
I
D(pulse)
*
1
0.4
A
Channel dissipation
Pch
150
mW
Channel temperature
Tch
150
°
C
Storage temperature
Tstg
55 to +150
°
C
Note:
1. PW
10
µ
s, duty cycle
1 %
Electrical Characteristics (Ta = 25°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V
(BR)DSS
20
--
--
V
I
D
= 10
µ
A, V
GS
= 0
Gate to source breakdown
voltage
V
(BR)GSS
±
10
--
--
V
I
G
=
±
100
µ
A, V
DS
= 0
Zero gate voltege drain
current
I
DSS
--
--
1.0
µ
A
V
DS
= 20 V, V
GS
= 0
Gate to source leak current
I
GSS
--
--
±
5.0
µ
A
V
GS
=
±
6.5V, V
DS
= 0
Gate to source cutoff voltage
V
GS(off)
0.5
--
1.5
V
I
D
= 10
µ
A, V
DS
= 5V
Static drain to source on state
resistance
R
DS(on)
--
0.8
1.1
I
D
= 100 mA
V
GS
= 4V
*
1
--
1.3
2.2
I
D
= 40 mA
V
GS
= 2.5V
*
1
Forward transfer admittance
|y
fs
|
0.22
0.35
--
S
I
D
= 100 mA
V
DS
= 10V
*
1
Input capacitance
Ciss
--
45
--
pF
V
DS
= 10V
Output capacitance
Coss
--
33
--
pF
V
GS
= 0
Reverse transfer capacitance Crss
--
9.6
--
pF
f = 1MHz
Turn-on delay time
t
d(on)
--
20
--
ns
V
GS
= 5V, I
D
= 100 mA
Rise time
t
r
--
60
--
ns
R
L
= 100
Turn-off delay time
t
d(off)
--
240
--
ns
Fall time
t
f
--
140
--
ns
Notes: 1. Pulse test
2. Marking is "ZL"
Cautions
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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