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Part Number 2SJ575

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2SJ575
Silicon P Channel MOS FET
High Speed Switching
ADE-208-740B (Z)
3rd.Edition.
June 1999
Features
·
Low on-resistance
R
DS
=2.8
typ. (V
GS
= -10 V , I
D
= -50 mA)
R
DS
=5.7
typ. (V
GS
= -4 V , I
D
= -50 mA)
·
4 V gate drive device.
·
Small package (MPAK)
Outline
1
2
3
1. Source
2. Gate
3. Drain
MPAK
2
3
1
D
S
G
2SJ575
2
Absolute Maximum Ratings (Ta = 25
°
C)
Item
Symbol
Ratings
Unit
Drain to source voltage
V
DSS
-30
V
Gate to source voltage
V
GSS
±
20
V
Drain current
I
D
-100
mA
Drain peak current
I
D(pulse)
Note1
-400
mA
Body-drain diode reverse drain current
I
DR
-100
mA
Channel dissipation
Pch
Note 2
400
mW
Channel temperature
Tch
150
°
C
Storage temperature
Tstg
­55 to +150
°
C
Note:
1. PW
10
µ
s, duty cycle
1%
2. Value on the alumina ceramic board (12.5x20x0.7mm)
Electrical Characteristics (Ta = 25
°
C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V
(BR)DSS
-30
--
--
V
I
D
= -100
µ
A, V
GS
= 0
Gate to source breakdown
voltage
V
(BR)GSS
±
20
--
--
V
I
G
=
±
100
µ
A, V
DS
= 0
Gate to source leak current
I
GSS
--
--
±
5
µ
A
V
GS
=
±
16 V, V
DS
= 0
Zero gate voltege drain
current
I
DSS
--
--
-1
µ
A
V
DS
= -30 V, V
GS
= 0
Gate to source cutoff voltage
V
GS(off)
-1.3
--
-2.3
V
I
D
= -10
µ
A, V
DS
= -5 V
Static drain to source on state R
DS(on)
--
2.8
3.3
I
D
= -50 mA,V
GS
= -10 V
Note 3
resistance
R
DS(on)
--
5.7
7.9
I
D
= -50 mA,V
GS
= -4 V
Note 3
Forward transfer admittance
|y
fs
|
68
105
--
mS
I
D
= -50 mA, V
DS
= -10 V
Note 3
Input capacitance
Ciss
--
25
--
pF
V
DS
= -10 V
Output capacitance
Coss
--
20
--
pF
V
GS
= 0
Reverse transfer capacitance Crss
--
8
--
pF
f = 1 MHz
Turn-on delay time
t
d(on)
--
10
--
ns
I
D
= -50mA, V
GS
= -10 V
Rise time
t
r
--
15
--
ns
R
L
= 200
Turn-off delay time
t
d(off)
--
40
--
ns
Fall time
t
f
--
45
--
ns
Note:
3. Pulse test
4. Marking is AP
2SJ575
3
Main Characteristics
-0.1
-1.0
-10
-50
-0.5
-0.4
-0.3
-0.2
-0.1
0
-2
-4
-6
-8
-10
-0.5
-0.4
-0.3
-0.2
-0.1
0
-2
-4
-6
-8
-10
800
600
400
200
0
50
100
150
200
V = -3 V
GS
Tc = ­25 °C
75 °C
Pulse Test
V = -10 V
Pulse Test
DS
-5
-1.0
-0.1
-0.01
-0.001
PW = 10 ms
(1 shot)
DC Operation
-5V
-4 V
-7 V -6 V
25 °C
Drain to Source Voltage V (V)
DS
Mavimum Safe Operation Area
Drain Current I (A)
D
Typical Output Characteristics
Drain to Source Voltage V (V)
DS
Gate to Source Voltage V (V)
GS
Typical Transfer Characteristics
Operation in this area
is limited by RDS(on)
Channel Dissipation *Pch (mW)
Ambient Temperature Ta ( °C)
Power vs. Temperature Derating
Drain Current I (A)
D
Drain Current I (A)
D
10 µs
100 µs
1 ms
-0.05
-0.2 -0.5
-2
-5
-20
-0.0005
-0.002
-0.005
-0.02
-0.05
-0.2
-0.5
-2
Ta=25 °C
*Value on the alumina ceramic boad (12.5x20x0.7mm)
Value on the alumina ceramic boad (12.5x20x0.7mm)
2SJ575
4
-1.0
-0.8
-0.6
-0.4
-0.2
0
-2
-4
-6
-8
-10
10
8
6
4
2
­40
0
40
80
120
160
0
I = -100mA
D
-10m A
Pulse Test
Pulse Test
I = -10m A, -50m A
D
V = -4 V
GS
-10 V
Gate to Source Voltage V (V)
GS
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
V (V)
DS(on)
Drain to Source Saturation Voltage
-0.01
-0.05
-0.02
50
20
10
2
5
1.0
0.5
-0.1
V = -4 V
GS
-10V
Pulse Test
Drain Current I (A)
D
Static Drain to Source on State
Resistance vs. Drain Current
Case Temperature Tc ( °C)
Static Drain to Source on State
Resistance vs. Temperature
Typical Transfer Characteristics
-50m A
-100m A
-10m A, -50m A, -100m A
-0.01
-0.02
-0.1
0.5
0.1
0.01
Drain Current I (A)
D
|yfs| (S)
Forward Transfer Admittance
-0.05
0.005
0.02
0.05
0.2
V = -10 V
Pulse Test
DS
Tc = ­25 °C
75 °C
25 °C
Static Drain to Source on State Resistance
()
DS(on)
R
Static Drain to Source on State Resistance
()
DS(on)
R
2SJ575
5
-0.5
-0.4
-0.3
-0.2
-0.1
0
-0.4
-0.8
-1.2
-1.6
-2.0
V = 0,5 V
GS
-5 V
Pulse Test
Switching Characteristics
Source to Drain Voltage V (V)
SD
Reverse Drain Current I (A)
DR
Reverse Drain Current vs.
Source to Drain Voltage
-10 V
Capacitance C (pF)
Drain to Source Voltage V (V)
DS
Typical Capacitance
vs. Drain to Source Voltage
1000
100
10
1
-0.1
-0.02
-0.01
Drain Current I (A)
D
Switching Time t (ns)
-0.05
5
2
20
50
200
500
V = -4 V, V = -10 V
PW = 5 µs, duty < 1 %
GS
DD
t f
r
t
d(on)
t
d(off)
t
0
-10
-20
-30
-40
-50
100
10
20
50
1
2
5
Ciss
Coss
Crss
V = 0
f = 1 MHz
GS
2SJ575
6
Vin Monitor
D.U.T.
Vin
-10 V
R
L
V
= ­10 V
DD
tr
td(on)
Vin
90%
90%
10%
10%
Vout
td(off)
Vout
Monitor
50
90%
10%
t
f
Switching Time Test Circuit
Waveforms
2SJ575
7
Package Dimensions
Unit: mm
0.16
0 ~ 0.1
0.3
+ 0.10
­ 0.06
0.4
+ 0.10
­ 0.05
0.95
0.95
1.9
2.95
+ 0.2
­ 0.2
2.8
+ 0.2
­ 0.6
0.65
+ 0.1
­ 0.3
1.5
0.65
+ 0.1
­ 0.3
1.1
+ 0.2
­ 0.1
Hitachi Code
EIAJ
JEDEC
MPAK
SC-59
TO-236Mod.
0.45
0.45
2SJ575
8
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor
products.
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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