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Part Number GS8640Z36T

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GS8640Z18/36T-300/250/200/167
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz­167 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.01 1/2006
1/25
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
· NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
· 2.5 V or 3.3 V +10%/­10% core power supply
· 2.5 V or 3.3 V I/O supply
· User-configurable Pipeline and Flow Through mode
· LBO pin for Linear or Interleave Burst mode
· Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
· Byte write operation (9-bit Bytes)
· 3 chip enable signals for easy depth expansion
· ZZ Pin for automatic power-down
· JEDEC-standard 100-lead TQFP package
· RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8640Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-300
-250
-200
-167
Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.3
3.3
2.5
4.0
3.0
5.0
3.5
6.0
ns
ns
Curr
(x18)
Curr
(x32/x36)
400
480
340
410
290
350
260
305
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
8.0
8.0
ns
ns
Curr
(x18)
Curr
(x32/x36)
285
330
245
280
220
250
210
240
mA
mA
*All GSI Technology packages are at least 5/6 RoHS compliant.
Packages listed with the additional "G" designator are 6/6 RoHS compliant.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
FT
V
DD
V
DD
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
AD
V
A
A
A
A
A
2M x 18
Top View
DQP
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GS8640Z18/36T-300/250/200/167
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Rev: 1.01 1/2006
2/25
© 2004, GSI Technology
GS8640Z18T Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
FT
V
DD
V
DD
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
AD
V
A
A
A
A
A
1M x 36
Top View
DQ
B
DQP
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
DQP
D
DQ
C
DQP
C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GS8640Z18/36T-300/250/200/167
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 1/2006
3/25
© 2004, GSI Technology
GS8640Z36T Pinout
TQFP Pin Descriptions
Symbol
Type
Description
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
Clock Input Signal
B
A
In
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
B
B
In
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
B
C
In
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
B
D
In
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
W
In
Write Enable; active low
E
1
In
Chip Enable; active low
E
2
In
Chip Enable; Active High. For self decoded depth expansion
E
3
In
Chip Enable; Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
DQ
A
I/O
Byte A Data Input and Output pins
DQ
B
I/O
Byte B Data Input and Output pins
DQ
C
I/O
Byte C Data Input and Output pins
DQ
D
I/O
Byte D Data Input and Output pins
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low
V
DD
In
Core power supply
V
SS
In
Ground
V
DDQ
In
Output driver power supply
NC
--
No Connect
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K
SA1
SA0
Burs
t
Counter
LBO
ADV
Memory
Array
E
3
E
2
E
1
G
W
B
D
B
C
B
B
B
A
CK
CKE
D
Q
FT
DQa
­
DQ
n
K
SA
1
'
SA
0
'
D
Q
Match
W
rit
e Addr
ess
Regist
er
2
W
rit
e Addr
ess
R
e
gist
er 1
W
r
ite
Dat
a
Regist
er 2
W
r
ite
Dat
a
R
e
gist
er 1
K
K
K
K
K
K
Se
nse Amps
Write Driver
s
Re
a
d
,
W
r
ite
an
d
Da
t
a Co
her
en
cy
Control Logic
FT
A
0
­An
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GS8640Z18/36 NBT SRAM Functional Block Diagram
GS8640Z18/36T-300/250/200/167
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Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
& B
D
) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
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Deselect
New Read
New Write
Burst Read
Burst Write
W
R
B
R
B
W
D
D
B
B
W
R
D
B
W
R
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline and Flow Through Read/Write Control State Diagram
W
R
Pipeline and Flow Through Read Write Control State Diagram
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Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+2)
Transition
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline Mode Data I/O State Diagram
Next State
State
Pipeline Mode Data I/O State Diagram
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High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for:
Pipeline and Flow Through Read Write Control State Diagram
Flow Through Mode Data I/O State Diagram
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Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th Bit Enable
PE
L
Activate DQPx I/Os (x18/x3672 mode)
H or NC
Deactivate DQPx I/Os (x16/x3272 mode)
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those this input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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Burst Counter Sequences
BPR 1999.05.18
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Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR
tZZH
tZZS
tKL
tKL
tKH
tKH
tKC
tKC
CK
ZZ
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
­0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
­0.5 to 4.6
V
V
I/O
Voltage on I/O Pins
­0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
­0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/­20
mA
I
OUT
Output Current on Any I/O Pin
+/­20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
­55 to 125
o
C
T
BIAS
Temperature Under Bias
­55 to 125
o
C
GS8640Z18/36T-300/250/200/167
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 1/2006
14/25
© 2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be ­2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8640Z18/36T-300/250/200/167
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V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
­0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
­0.3
--
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be ­2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
­0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
­0.3
--
0.3*V
DD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be ­2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
T
A
­40
25
85
°C
2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be ­2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8640Z18/36T-300/250/200/167
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Rev: 1.01 1/2006
16/25
© 2004, GSI Technology
20% tKC
V
SS
­ 2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
Capacitance
o
C, f = 1 MH
Z
, V
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
­ 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
(T
A
= 25
= 2.5 V)
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
­2 uA
2 uA
ZZInput Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
­1 uA
­1 uA
1 uA
100 uA
Output Leakage Current (x36/x72)
I
OL
Output Disable, V
OUT
= 0 to V
DD
­1 uA
1 uA
Output Leakage Current (x18)
I
OL
Output Disable, V
OUT
= 0 to V
DD
­1 uA
1 uA
Output High Voltage
V
OH2
I
OH
= ­8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
= ­8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
GS8640Z18/36T-300/250/200/167
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Rev: 1.01 1/2006
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© 2004, GSI Technology
Operating Currents
Parameter
Test Conditions
Mode
Symbol
-300
-250
-200
-167
Unit
0
to
70°C
­40
to
85°C
0
to
70°C
­40
to
85°C
0
to
70°C
­40
to
85°C
0
to
70°C
­40
to
85°C
Operating
Current
Device Selected;
All other inputs
V
IH
or
V
IL
Output open
(x32/
x36)
Pipeline
I
DD
I
DDQ
420
60
440
60
360
50
380
50
310
40
330
40
270
35
290
35
mA
Flow
Through
I
DD
I
DDQ
300
30
320
30
255
25
275
25
230
20
250
20
220
20
240
20
mA
(x18)
Pipeline
I
DD
I
DDQ
370
30
390
30
315
25
335
25
270
20
290
20
240
20
260
20
mA
Flow
Through
I
DD
I
DDQ
270
15
290
15
230
15
250
15
205
15
225
15
195
15
215
15
mA
Standby
Current
ZZ
V
DD
­ 0.2 V
--
Pipeline
I
SB
100
120
100
120
100
120
100
120
mA
Flow
Through
I
SB
100
120
100
120
100
120
100
120
mA
Deselect
Current
Device Deselected;
All other inputs
V
IH
or
V
IL
--
Pipeline
I
DD
150
165
140
155
130
146
125
140
mA
Flow
Through
I
DD
135
150
125
140
120
135
120
135
mA
GS8640Z18/36T-300/250/200/167
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Rev: 1.01 1/2006
18/25
© 2004, GSI Technology
Notes:
1. I
DD
and I
DDQ
apply to any combination of V
DD3
, V
DD2
, V
DDQ3
, and V
DDQ2
operation.
2. All parameters listed are worst case scenario.
AC Electrical Characteristics
Parameter
Symbol
-300
-250
-200
-167
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.3
--
4.0
--
5.0
--
6.0
--
ns
Clock to Output Valid
tKQ
--
2.3
--
2.5
--
3.0
--
3.5
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
1.5
--
ns
Setup time
tS
1.1
--
1.2
--
1.4
--
1.5
--
ns
Hold time
tH
0.1
--
0.2
--
0.4
--
0.5
--
ns
Flow
Through
Clock Cycle Time
tKC
5.5
--
6.5
--
7.5
--
8.0
--
ns
Clock to Output Valid
tKQ
--
5.5
--
6.5
--
7.5
--
8.0
ns
Clock to Output Invalid
tKQX
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock to Output in Low-Z
tLZ
1
3.0
--
3.0
--
3.0
--
3.0
--
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Clock HIGH Time
tKH
1.0
--
1.3
--
1.3
--
1.3
--
ns
Clock LOW Time
tKL
1.2
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
--
2.3
--
2.5
--
3.0
--
3.5
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
ns
G to output in High-Z
tOHZ
1
--
2.3
--
2.5
--
3.0
--
3.0
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
ns
GS8640Z18/36T-300/250/200/167
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 1/2006
19/25
© 2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
GS8640Z18/36T-300/250/200/167
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Rev: 1.01 1/2006
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© 2004, GSI Technology
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
Read C
Write D
writeno-op
Read E
Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
D
E
D(A)
D(D)
Q(E)
Q(B)
Q(C)
CK
A
CKE
E*
ADV
W
Bn
DQ
GS8640Z18/36T-300/250/200/167
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Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E
ADV
W
Bn
A0­An
DQ
G
GS8640Z18/36T-300/250/200/167
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TQFP Package Drawing (Package T)
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
--
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
--
0.65
--
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
--
1.00
--
Y
Coplanarity
0.10
Lead Angle
0
°
--
7
°
GS8640Z18/36T-300/250/200/167
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Ordering Information--GSI NBT Synchronous SRAM
Org
Part Number
1
Type
2
Package
Speed
3
(M
Hz/ns)
T
A
4
Status
4M x 18
GS8640Z18T-300
NBT Pipeline/Flow Through
TQFP
300/5.5
C
4M x 18
GS8640Z18T-250
NBT Pipeline/Flow Through
TQFP
250/6.5
C
4M x 18
GS8640Z18T-200
NBT Pipeline/Flow Through
TQFP
200/7.5
C
4M x 18
GS8640Z18T-167
NBT Pipeline/Flow Through
TQFP
167/8
C
2M x 36
GS8640Z36T-300
NBT Pipeline/Flow Through
TQFP
300/5.5
C
2M x 36
GS8640Z36T-250
NBT Pipeline/Flow Through
TQFP
250/6.5
C
2M x 36
GS8640Z36T-200
NBT Pipeline/Flow Through
TQFP
200/7.5
C
2M x 36
GS8640Z36T-167
NBT Pipeline/Flow Through
TQFP
167/8
C
4M x 18
GS8640Z18T-300I
NBT Pipeline/Flow Through
TQFP
300/5.5
I
4M x 18
GS8640Z18T-250I
NBT Pipeline/Flow Through
TQFP
250/6.5
I
4M x 18
GS8640Z18T-200I
NBT Pipeline/Flow Through
TQFP
200/7.5
I
4M x 18
GS8640Z18T-167I
NBT Pipeline/Flow Through
TQFP
167/8
I
2M x 36
GS8640Z36T-300I
NBT Pipeline/Flow Through
TQFP
300/5.5
I
2M x 36
GS8640Z36T-250I
NBT Pipeline/Flow Through
TQFP
250/6.5
I
2M x 36
GS8640Z36T-200I
NBT Pipeline/Flow Through
TQFP
200/7.5
I
2M x 36
GS8640Z36T-167I
NBT Pipeline/Flow Through
TQFP
167/8
I
4M x 18
GS8640Z18GT-300
NBT Pipeline/Flow Through
RoHS-compliant TQFP
300/5.5
C
4M x 18
GS8640Z18GT-250
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/6.5
C
4M x 18
GS8640Z18GT-200
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/7.5
C
4M x 18
GS8640Z18GT-167
NBT Pipeline/Flow Through
RoHS-compliant TQFP
167/8
C
2M x 36
GS8640Z36GT-300
NBT Pipeline/Flow Through
RoHS-compliant TQFP
300/5.5
C
2M x 36
GS8640Z36GT-250
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/6.5
C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8640Z36T-167IT.
2. All GSI Technology packages are at least 5/6 RoHS compliant. Packages listed with the additional "G" designator are 6/6 RoHS compliant.
3. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
4. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
GS8640Z18/36T-300/250/200/167
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2M x 36
GS8640Z36GT-200
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/7.5
C
2M x 36
GS8640Z36GT-167
NBT Pipeline/Flow Through
RoHS-compliant TQFP
167/8
C
4M x 18
GS8640Z18GT-300I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
300/5.5
I
4M x 18
GS8640Z18GT-250I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/6.5
I
4M x 18
GS8640Z18GT-200I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/7.5
I
4M x 18
GS8640Z18GT-167I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
167/8
I
2M x 36
GS8640Z36GT-300I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
300/5.5
I
2M x 36
GS8640Z36GT-250I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
250/6.5
I
2M x 36
GS8640Z36GT-200I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
200/7.5
I
2M x 36
GS8640Z36GT-167I
NBT Pipeline/Flow Through
RoHS-compliant TQFP
167/8
I
Ordering Information--GSI NBT Synchronous SRAM
Org
Part Number
1
Type
2
Package
Speed
3
(M
Hz/ns)
T
A
4
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8640Z36T-167IT.
2. All GSI Technology packages are at least 5/6 RoHS compliant. Packages listed with the additional "G" designator are 6/6 RoHS compliant.
3. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
4. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
72Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
8640Zxx_r1
· Creation of new datasheet
8640Zxx_r1; 8640Zxx_r1_01
Content
· Corrected erroneous timing diagrams
GS8640Z18/36T-300/250/200/167
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