SPARClite Superscaler
Embedded RISC Processor
MB86860
Instruction
Cache
(16 KB/4-way)
Data Cache
(16 KB/4-way)
PC
Unit
Fetch
Decode/
Schedule/
Exception
Handling
Align
DSU
MUX
Description
w
ALU1
ALU2
Load/
Store
Register File
BIU
I-ADR
I-DATA
D-ADR
D-DATA
PLL
Buffer Unit
PLL
DMAC
SDRAM I/F
SP
ARClite Bus I/F
ROM, I/O
SDRAM
The MB86860, based on the SPARC architecture from
SPARC International, Inc., is a powerful embedded
microprocessor that features a superscalar RISC CPU core
and 64-bit SDRAM interface, along with 16 KB of each of
I-cache and D-cache. With its 200-MHz superscalar CPU core
capable of two simultaneous integer instructions, the device
can perform integer arithmetic operations at a rate of
approximately 420 MIPS, the highest level in its class.
Based on the SPARC architecture, the MB86860 series
performs integer arithmetic operations compatible with
conventional SPARC instructions running on Sun
workstations. The MB86860 series has SPARClite buses
compatible with the other SPARClite family devices so it
can use existing hardware design resources such as peripheral
chipsets, etc.
The MB86860 is targeted at network system applications,
including hubs, routers, and systems that support ATM
technology. The processor is also well suited for color
printer applications. The MB86860 is available
in a 352-pin BGA package.
CPU Core
Integer Unit
64-bit/100 MHz Bus
64/32
64/32
64
64
64
· Internal Operating Frequency 200 MHz (max)
· 16 KB Instruction Cache (4-way)
· 16 KB Data Cache (4-way)
· PC-100 Compatible SDRAM Interface
· 8/16/32/64-bit Data Bus
· 2 DMA Channels
· Power-Down Mode
Features
w
SPARClite Superscalar Embedded RISC Processor
© 1999 Fujitsu Microelectronics, Inc.
All company and product names are trademarks or
registered trademarks of their respective owners.
Printed in the U.S.A. EC-FS-20810-6/99
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters
3545 North First Street, San Jose, California 95134-1804
Tel: (800) 866-8608 Fax: (408) 922-9179
E-mail: fmicrc@fmi.fujitsu.com Web Site: http://www.fujitsumicro.com
Conforms to SPARC V8 architecture
Compatible with other
SPARClite processors
Internal operating frequency maximum: 200 MHz
x1, x2, x3, x4, x5
2-issue super-scalar architecture
Higher performance
16 KB 4-way instruction cache
Faster local processing
16 KB 4-way data cache
Faster local processing
Power down mode
Saves power
Bi-endian support
Easy software development
Break function (instruction address/
external pins/software/single step)
Speeds up design debug
16-depth address trace buffer
Easier debug
Single step operation
Easier debug
64/32 bit data bus widths
Design flexibility and cost savings
Maximum 100 MHz operation
PC-100 compatibility,
faster memory access
Auto/self-refresh support
No glue logic
Parity function support
Flexible memory support
4-column instruction Buffer
Minimal I/O latency
4-column x 2 read buffer
Minimal I/O latency
16-column write buffer
Minimal I/O latency
CPU Core
Features
Benefits
Debug Support Functions
Features
Benefits
Data Buffer Module
Features
Benefits
SDRAM Interface
Features
Benefits
8/16/32/64-bit data bus
Backward hardware compatible
with other SPARClite devices,
design flexibility, cost savings
Burst-mode support
SPARClite Bus Interface
Features
Benefits
2 DMA channels
External bus-master support
Simultaneous operation: 1 channel
Bus-Bridge DMA
Features
Benefits
Other
Features
Benefits
Core: 2.5V
Saves power
I/O Pins: 3.3V
Saves power
352-pin low-profile BGA package, no heat sink
Lower device cost
PDF 
ZIP