DATA SHEET
Sept. 1995
Edition 3.0b
Copyright
E
1995 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.
MB510
2.7GHz TWO MODULUS PRESCALER
2.7GHz TWO MODULUS PRESCALER
The Fujitsu MB510 is an ultra high speed, two modulus prescaler that forms a
Phase Locked Loop (PLL) when combined with a frequency synthesizer such as
the Fujitsu MB87001A. It divides the input frequency by the modulus of 128/144
or 256/272, and operates at a low power supply current of 10mA at 5.0V.
Through the use of Fujitsu's Advanced Process Technology, the MB510 achieves
extremely small stray capacitance from its internal elements.
FEATURES
S
High Frequency Operation:
2.7GHz max.
S
Power Dissipation:
50mW typ.
S
Pulse Swallow Function:
128/144, 256/272
S
Wide Operation Temperature:
-40
°
C to +85
°
C
S
Stable Output Amplitude:
V
OUT
= 1.6V
pp
typ.
S
Builtin Termination Resistor
S
Complete PLL synthesizer circuit with the Fujitsu MB87001A PLL
synthesizer IC
S
Package
Standard 8-pin Flat Package
(Suffix: PF)
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
V
CC
0.5 to +7.0
V
Input Voltage
V
IN
0.5 to V
CC
V
Output Current
I
O
10
mA
Storage Temperature
T
STG
55 to +125
°
C
Note:
Permanent device damage may occur if the above Absolute Maximum Ratings
are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PLASTIC PACKAGE
FPT-08P-M01
PIN ASSIGNMENT
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
IN
V
CC
SW
OUT
IN
NC
GND
MC
1
2
3
4
5
6
7
TOP VIEW
8
MB510
2
MC
Divide Ratio
H
L
1/128
1/144
Note:
SW: H = V
CC
, L = open
MC: H = 2.0V to V
CC
, L = GND to 0.8V
H
1/256
L
1/272
SW
H
H
L
L
D
C
Q
D
C
Q
Q
D
CM
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
SW
Q
Q
INPUT BUFFER
IN
IN
MC
OUTPUT
BUFFER
OUT
SW
Figure 1. MB510 Block Diagram
PIN DESCRIPTION
Pin Number
Symbol
Function
1
IN
Input
2
V
CC
DC Supply Voltage
3
SW
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
NC
Non Connection
8
IN
Complementary Input
MB510
3
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Output Current
I
O
1.2
mA
Ambient Temperature
T
A
40
+85
°
C
Load Capacitance
C
L
8
pF
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Condition
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Supply Curent
I
CC
10.0
15.0
mA
Output Amplitude
V
O
Built-in a termination
resistor.
Load capacitance = 8pF
1.0
1.6
V
pp
Input Frequency
f
IN
With input coupling
capacitor 1000pF
10
2700
MHz
Input Signal Amplitude
P
IN
f
IN
= 10 to 2200MHz
10
10
dBm
Input Signal Amplitude
P
IN
f
IN
= 2200 to 2700MHz
4
10
dBm
High Level Input Voltage for MC
Input
V
IHM
2.0
V
Low Level Input Voltage for MC
Input
V
ILM
0.8
V
High Level Input Voltage for SW
Input
V
IHS
*
V
CC
0.1
V
CC
V
CC
+0.1
V
Low Level Input Voltage for SW
Input
V
ILS
Open
V
High Level Input Current for MC
Input
I
IHM
V
IH
= 2.0V
0.4
mA
Low Level Input Current for MC
Input
I
ILM
V
IL
= 0.8V
0.2
mA
Modulus Set-up Time MC to OUT
t
SET
16
26
ns
Note: *Design
Guarantee
MB510
4
Sampling scope input point
for input waveform
P.G.
C
1
C
2
50
MC Input
C
L
C
3
V
CC
= +5.0V + 10%
Sampling scope prober point
for output waveform
C
1
: 1000pF
C
2
: 1000pF
C
3
: 0.1
µ
F
C
L
: 8pF (including scope and jig capacitance)
V
CC
SW
OUT
GND
MC
IN
IN
Figure 2. Test Circuit
800
600
500
400
300
200
100
10
20
50
100
200
500 1000 2000
INPUT FREQUENCY (MHz)
MINIMUM INPUT
SIGNAL
AMPLITUDE
(mVpp)
V
CC
= 5.0V
T
A
= 25
°
C
Figure 3. Input Signal Amplitude vs. Input Frequency
MB510
5
128
144
IN
OUT
MC
64
64
64
80
64 64 64 64
64 64 80 64 80 64 80
t
SET
t
SET
Note: When divide of 144 is selected, positive pulse is applied by 16 to 80.
The typical set up time is 16 ns from the MC signal input to the timing of change of prescaler divide ratio.
Example: Divide ratio = 128/144
TIMING CHART (2 MODULUS)
16 15 14 13 12 11 10 9
1
2
3 4
5 6
7 8
MB 87001A
1
2
3
4
5
6
7
8
MB 510
VCO
V
CC
C
1
V
CC
V
CC
C
2
X1
0.047
µ
F
Data
Clock
LE
47K
47K
47K
1000pF
V
CC
1000pF
1000pF
2.2K
1000pF
33K
100K
V
CC
12K
12K
10K
V
SX
(Max. 8V)
10K
OUTPUT
X1
: 12.8MHz X'tal
V
CC
: 5V + 10%
V
SX
: 8V max.
C
1
, C
2
: depends on crystal oscillator
Lock
Det.
10K
Figure 4. Typical Application Example
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