© 2000 Fairchild Semiconductor Corporation
DS010965
www.fairchildsemi.com
October 1991
Revised April 2000
SCAN18541
T Non-I
n
ver
ti
ng
Li
ne Driv
er w
i
th 3-
ST
A
T
E O
u
t
put
s
SCAN18541T
Non-Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18541T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control sig-
nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
s
IEEE 1149.1 (JTAG) Compliant
s
Dual output enable signals per byte
s
3-STATE outputs for bus-oriented applications
s
9-bit data busses for parity applications
s
Reduced-swing outputs source 32 mA/sink 64 mA
s
Guaranteed to drive 50
transmission line to TTL input
levels of 0.8V and 2.0V
s
TTL compatible inputs
s
25 mil pitch SSOP (Shrink Small Outline Package)
s
Includes CLAMP and HIGHZ instructions
s
Member of Fairchild's SCAN Products
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Names
Truth Tables
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
Z
=
High Impedance
Order Number
Package Number
Package Description
SCAN18541TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names
Description
AI
(08)
Input Pins, A Side
BI
(08)
Input Pins, B Side
AOE
1
, AOE
2
3-STATE Output Enable Input Pins,
A Side
BOE
1
, BOE
2
3-STATE Output Enable Input Pins,
B Side
AO
(08)
Output Pins, A Side
AO
(08)
Output Pins, B Side
Inputs
AO
(08)
AOE
1
AOE
2
AI
(08)
L
L
H
H
H
X
X
Z
X
H
X
Z
L
L
L
L
Inputs
BO
(08)
BOE
1
BOE
2
BI
(08)
L
L
H
H
H
X
X
Z
X
H
X
Z
L
L
L
L
3
www.fairchildsemi.com
SCAN18541
T
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001. The two least signifi-
cant bits of this captured value (01) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18541T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a "pseudo ID" code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
MSB
LSB
Scan Cell TYPE1
Scan Cell TYPE2
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
All Others
BYPASS
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