February 1984
Revised February 1999
MM74HCT273
Octal
D-
T
ype
Fl
ip-
F
lop
wit
h
C
l
ear
© 1999 Fairchild Semiconductor Corporation
DS005760.prf
www.fairchildsemi.com
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Description
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive simi-
lar to LS-TTL with the low standby power of CMOS.
These positive edge-triggered flip-flops have a common
clock and clear-independent Q outputs. Data on a D input,
having the specified set-up and hold time, is transferred to
the corresponding Q output on the positive-going transition
of the clock pulse. The asynchronous clear forces all out-
puts LOW when it is LOW.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to V
CC
and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Features
s
Typical propagation delay: 20 ns
s
Low quiescent current: 80
µ
A maximum (74HCT series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Order Number
Package Number
Package Description
MM74HCT273WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
MM
74HCT273
Truth Table
(Each Flip-Flop)
H
=
HIGH Level (steady-state)
L
=
LOW Level (steady-state)
X
=
Don't Care
=
Transition from LOW-to-HIGH level
Q0
=
The level of Q before the indicated steady-state input
conditions were established.
Logic Diagram
Inputs
Outputs
Clear
Clock
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
3
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MM74HCT273
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power dissipation temperature derating--plastic "N" package:
-
12
mW/
°
C from 65
°
C to 85
°
C.
DC Electrical Characteristics
V
CC
=
5V
±
10% unless otherwise specified
Note 4: Measured per pin, all other inputs held at V
CC
or GND.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5V to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
±
20 mA
DC Output Current, per Pin (I
OUT
)
±
25 mA
DC V
CC
or GND Current, per Pin (I
CC
)
±
50 mA
Storage Temperature Range (T
STG
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
Min
Max
Units
Supply Voltage (V
CC
)
4.5
5.5
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
°
C
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Symbol
Parameter
Conditions
T
A
=
25
°
C
T
A
=
-
40
°
C to 85
°
C T
A
=
-
55
°
C to 125
°
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0
2.0
2.0
V
Input Voltage
V
IL
Maximum LOW Level
0.8
0.8
0.8
V
Input Voltage
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
=
20
µ
A
V
CC
V
CC
-
0.1
V
CC
-
0.1
V
CC
-
0.1
V
|I
OUT
|
=
4.0 mA, V
CC
=
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
=
4.8 mA, V
CC
=
5.5V
5.2
4.98
4.84
4.7
V
V
OL
Minimum LOW Level
V
IN
=
V
IH
or V
IL
Voltage
|I
OUT
|
=
20
µ
A
0
0.1
0.1
0.1
V
|I
OUT
|
=
4.0 mA, V
CC
=
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
=
4.8 mA, V
CC
=
5.5V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND,
±
0.1
±
1.0
±
1.0
µ
A
Current
V
IH
or V
IL
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
8
80
160
µ
A
Supply Current
I
OUT
=
0
µ
A
V
IN
=
2.4V or 0.5V (Note 4)
0.6
0.8
0.9
mA
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4
MM
74HCT273
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
V
CC
=
5.0V
±
10%, C
L
=
50 pF, t
r
=
t
f
=
6 ns unless otherwise specified
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
2
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limits
f
MAX
Maximum Operating Frequency
68
30
MHz
t
PHL
, t
PLH
Maximum Propagation Delay from Clock to Q
18
30
ns
t
PHL
, t
PLH
Maximum Propagation Delay from Clear to Q
21
30
ns
t
REM
Minimum Removal Time, Clear to Clock
-
1
5
ns
t
S
Minimum Set-Up Time D to Clock
6
20
ns
t
H
Minimum Hold Time Clock to D
-
3
5
ns
t
W
Minimum Pulse Width Clock or Clear
10
16
ns
Symbol
Parameter
Conditions
T
A
=
25
°
C
T
A
=
-
40
°
C to 85
°
C T
A
=
-
55
°
C to 125
°
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
68
27
21
18
MHz
Frequency
t
PHL
, t
PLH
Maximum Propagation
22
37
46
56
ns
Delay from Clock to Q
t
PHL
, t
PLH
Maximum Propagation
25
35
44
52
ns
Delay from Clear to Q
t
REM
Minimum Removal
-
1
5
6
7
ns
Time Clear to Clock
t
S
Minimum Set-Up Time
6
20
25
30
ns
D to Clock
t
H
Minimum Hold Time
-
3
5
5
5
ns
Clock to D
t
W
Minimum Pulse Width
10
16
25
30
ns
Clock or Clear
t
r
, t
f
Maximum Input Rise
500
500
500
ns
and Fall Time, Clock
t
THL
, t
TLH
Maximum Output Rise
11
15
19
22
ns
and Fall Time
C
PD
Power Dissipation
(Per Flip-Flop)
50
pF
Capacitance (Note 5)
C
IN
Maximum Input
6
10
10
10
pF
Capacitance
5
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MM74HCT273
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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