January 1992
Revised May 1999
MM74HC594 8-Bi
t Shif
t Regi
ster
wit
h
O
u
t
put
Regi
ster
s
© 1999 Fairchild Semiconductor Corporation
DS010915.prf
www.fairchildsemi.com
MM74HC594
8-Bit Shift Register with Output Registers
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. Separate
clocks and direct overriding clears are provided for both the
shift register and the storage register. The shift register has
a direct-overriding clear, serial input, and serial output
(standard) pins for cascading. Both the shift register and
storage register use positive-edge triggered clocks. If both
clocks are connected together, the shift register state will
always be one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Low quiescent current: 80
µ
A maximum
s
Low input current: 1
µ
A maximum
s
8-bit serial-in, parallel-out shift register with storage
s
Wide operating voltage range: 2V to 6V
s
Cascadable
s
Shift register has direct clear
s
Guaranteed shift frequency: DC to30 MHz
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Truth Table
Order Number
Package Number
Package Description
MM74HC594M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
MM74HC594N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
RCK
SCK
SCLR RCLR
Function
X
X
X
L
Storage Register cleared
X
X
L
X
Shift Register cleared
Q'
H
=
0
X
H
H
Shift Register clocked
Q
N
=
Q
n
-
1
, Q
0
=
SER
X
H
H
Contents of Shift
Register transferred
to output latches
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2
MM
74HC594
Logic Diagram
3
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MM74HC594
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operation
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating--plastic "N" package:
-
12
mW/
°
C from 65
°
C to 85
°
C.
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
±
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
±
20 mA
DC Output Current, per pin (I
OUT
)
±
35 mA
DC V
CC
or GND Current, per pin (I
CC
)
±
70 mA
Storage Temperature Range (T
STG
)
-
65
°
C to
+
150
°
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
-
40
+
85
°
C
Input Rise or Fall Times
(t
r
, t
f
)
V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
T
A
=
-
40 to 85
°
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
6.0V
4.2
4.2
V
IL
Maximum LOW Level
2.0V
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
6.0V
1.8
1.8
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
V
Output Voltage
|I
OUT
|
20
µ
A
2.0V
2.0
1.9
1.9
4.5V
4.5
4.4
4.4
6.0V
6.0
5.9
5.9
Q'
H
V
IN
=
V
IH
or V
IL
V
|I
OUT
|
4.0 mA
4.5V
4.7
3.98
3.84
|I
OUT
|
5.2 mA
6.0V
5.2
5.48
5.34
Q
A
thru Q
H
V
IN
=
V
IH
or V
IL
V
|I
OUT
|
6.0 mA
4.5V
4.2
3.98
3.84
|I
OUT
|
7.8 mA
6.0V
5.7
5.48
5.34
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
V
Output Voltage
|I
OUT
|
20
µ
A
2.0V
0
0.1
0.1
4.5V
0
0.1
0.1
6.0V
0
0.1
0.1
Q'
H
V
IN
=
V
IH
or V
IL
V
|I
OUT
|
4.0 mA
4.5V
0.2
0.26
0.33
|I
OUT
|
5.2 mA
6.0V
0.2
0.26
0.33
Q
A
thru Q
H
V
IN
=
V
IH
or V
IL
V
|I
OUT
|
6.0 mA
4.5V
0.2
0.26
0.33
|I
OUT
|
7.8 mA
6.0V
0.2
0.26
0.33
I
IN
Maximum Input
V
IN
=
V
CC
or GND
6.0V
±
0.1
±
1.0
µ
A
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
µ
A
Supply Current
I
OUT
=
0
µ
A
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4
MM
74HC594
AC Electrical Characteristics
V
CC
= 2.0V to 6.0V, C
L
= 50 pF, t
r
= t
f
= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
-
40
°
C to
+
85
°
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
C
L
=
50 pF
2.0V
6
4.8
MHz
Frequency
4.5V
30
24
6.0V
35
28
t
PHL
, t
PLH
Maximum Propagation Delay
C
L
=
50 pF
2.0V
150
185
ns
from SCK to Q'
H
4.5V
30
37
6.0V
25
31
t
PHL
, t
PLH
Maximum Propagation Delay
C
L
=
50 pF
2.0V
150
185
ns
from RCK to Q
A
thru Q
H
C
L
=
150 pF
2.0V
200
250
C
L
=
50 pF
4.5V
30
37
ns
C
L
=
150 pF
4.5V
40
50
C
L
=
50 pF
6.0V
25
31
ns
C
L
=
150 pF
6.0V
34
43
t
PHL
, t
PLH
Maximum Propagation Delay
2.0V
150
185
ns
from SCLR to Q'
H
4.5V
30
37
6.0V
25
31
t
PHL
Maximum Propagation Delay
C
L
=
50 pF
2.0V
125
155
ns
from RCLR to Q
A
thru Q
H
4.5V
25
31
6.0V
21
26
C
L
=
150 pF
2.0V
200
250
ns
4.5V
40
50
6.0V
34
43
t
S
SCLR LOW to RCK
2.0V
50
63
ns
4.5V
10
13
6.0V
9
11
t
S
RCLR HIGH to SCK
2.0V
5
5
ns
4.5V
5
5
6.0V
5
5
t
S
Minimum Setup Time
2.0V
90
110
ns
from SER to SCK
4.5V
18
22
6.0V
15
19
t
R
Minimum Removal Time
2.0V
20
20
ns
from SCLR to SCK
4.5V
10
10
6.0V
10
10
t
S
Minimum Setup Time
2.0V
90
110
ns
from SCK to RCK
4.5V
18
22
6.0V
15
19
t
H
Minimum Hold Time
2.0V
5
5
ns
SER to SCK
4.5V
5
5
6.0V
5
5
t
W
Minimum Pulse Width
2.0V
100
125
ns
of SCK or SCLR or
4.5V
20
25
RCK or RCLR
6.0V
17
21
t
r
, t
f
Maximum Input Rise and
2.0V
1000
1000
ns
Fall Time, Clock
4.5V
500
500
6.0V
400
400
t
THL
, t
TLH
Maximum Output
2.0V
60
75
ns
Rise and Fall Time
4.5V
12
15
Q
A
- Q
H
6.0V
10
13
t
THL
, t
TLH
Maximum Output
2.0V
75
95
ns
Rise and Fall Time
4.5V
15
19
Q'
H
6.0V
13
16
5
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MM74HC594
AC Electrical Characteristics
(Continued)
Note 5: C
PD
determines the no load dynamic power consumption, and the no load dynamic current consumption.
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
-
40
°
C to
+
85
°
C
Units
Typ
Guaranteed Limits
C
PD
Power Dissipation Capacitance, G
=
V
CC
90
pF
Outputs Enabled (Note 5)
G
=
GND
150
C
IN
Maximum Input Capacitance
5
10
10
pF
C
OUT
Maximum Output Capacitance
15
20
20
pF
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