Š2004 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev.1.0.4

Features

ˇ Internal Avalanche Rugged Sense FET
ˇ Consumes only 0.65W at 240VAC & 0.3W load with

Advanced Burst-Mode Operation

ˇ Frequency Modulation for low EMI
ˇ Precision Fixed Operating Frequency
ˇ Internal Start-up Circuit
ˇ Pulse by Pulse Current Limiting
ˇ Abnormal Over Current Protection
ˇ Over Voltage Protection
ˇ Over Load Protection
ˇ Internal Thermal Shutdown Function
ˇ Auto-Restart Mode
ˇ Under Voltage Lockout
ˇ Low Operating Current (3mA)
ˇ Adjustable Peak Current Limit
ˇ Built-in Soft Start

Applications

ˇ SMPS for VCR, SVR, STB, DVD & DVCD
ˇ SMPS for Printer, Facsimile & Scanner
ˇ Adaptor for Camcorder

Description

The FSDx0365RN(x stands for L, M) are integrated Pulse
Width Modulators (PWM) and Sense FETs specifically
designed for high performance offline Switch Mode Power
Supplies (SMPS) with minimal external components. Both
devices are integrated high voltage power switching regula-
tors which combine an avalanche rugged Sense FET with a
current mode PWM control block. The integrated PWM con-
troller features include: a fixed oscillator with frequency
modulation for reduced EMI, Under Voltage Lock Out
(UVLO) protection, Leading Edge Blanking (LEB), opti-
mized gate turn-on/turn-off driver, Thermal Shut Down
(TSD) protection, Abnormal Over Current Protection
(AOCP) and temperature compensated precision current
sources for loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or
RCC switching converter solution, the FSDx0365RN reduce
total component count, design size, weight and at the same
time increase efficiency, productivity, and system reliability.
Both devices are a basic platform well suited for cost effec-
tive designs of flyback converters.

Table 1. Notes: 1. Typical continuous power in a non-ven-

tilated enclosed adapter measured at 50

C ambient. 2.

Maximum practical continuous power in an open frame

design at 50

C ambient. 3. 230 VAC or 100/115 VAC with

doubler.

Typical Circuit

Figure 1. Typical Flyback Application

OUTPUT POWER TABLE

PRODUCT

230VAC

15%

(3)

85-265VAC

Adapt-

(1)

Open

Frame

(2)

Adapt-

(1)

Open

Frame

(2)

FSDL321

11W

17W

12W

FSDH321

11W

17W

12W

FSDL0165RN

13W

23W

11W

17W

FSDM0265RN

16W

27W

13W

20W

FSDH0265RN

16W

27W

13W

20W

FSDL0365RN

19W

30W

16W

24W

FSDM0365RN

19W

30W

16W

24W

FSDL0165RL

13W

23W

11W

17W

FSDM0265RL

16W

27W

13W

20W

FSDH0265RL

16W

27W

13W

20W

FSDL0365RL

19W

30W

16W

24W

FSDM0365RL

19W

30W

16W

24W

Drain

Source

Vstr

Vfb

Vcc

PWM

OUT

Ipk

FSDL0365RN, FSDM0365RN

Green Mode Fairchild Power Switch (FPS

)

FSDL0365RN, FSDM0365RN

Pin Definitions

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Number

Pin Name

Pin Function Description

GND

Sense FET source terminal on primary side and internal control ground.

Vcc

Positive supply voltage input. Although connected to an auxiliary transform-
er winding, current is supplied from pin 5 (Vstr) via an internal switch during
startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and de-
vice power is supplied via the auxiliary transformer winding.

Vfb

The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and op-
tocoupler are typically connected externally. A feedback voltage of 6V trig-
gers over load protection (OLP). There is a time delay while charging
between 3V and 6V using an internal 5uA current source, which prevents
false triggering under transient conditions but still allows the protection
mechanism to operate under true overload conditions.

Ipk

Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current
source is diverted to the parallel combination of an internal 2.8k

resistor

and any external resistor to GND on this pin to determine the current limit.
If this pin is tied to Vcc or left floating, the typical current limit will be 2.15A.

Vstr

This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is disabled.

6, 7, 8

Drain

The Drain pin is designed to connect directly to the primary lead of the trans-
former and is capable of switching a maximum of 650V. Minimizing the
length of the trace connecting this pin to the transformer will decrease leak-
age inductance.

GND

Vcc

Vfb

Ipk

Vstr

Drain

8DIP

8LSOP

FSDL0365RN, FSDM0365RN

Absolute Maximum Ratings

(Ta=25

C, unless otherwise specified)

Note:

1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L = 51mH, starting Tj = 25

3. L = 13

H, starting Tj = 25

4. Vsd is shutdown feedback voltage ( see Protection Section in Electrical Characteristics )

Thermal Impedance

Note:

1. Free standing with no heatsink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 0.36 sq. inch(232mm2), 2 oz.(610g/m2) copper clad.

Characteristic

Symbol

Value

Unit

Drain Current Pulsed

(1)

12.0

Single Pulsed Avalanche Energy

(2)

127

Maximum Supply Voltage

CC,MAX

Analog Input Voltage Range

-0.3 to V

Total Power Dissipation

1.56

Operating Junction Temperature.

+150

Operating Ambient Temperature.

-25 to +85

Storage Temperature Range.

STG

-55 to +150

Parameter

Symbol

Value

Unit

8DIP

Junction-to-Ambient Thermal

(1)

85.74

C/W

(3)

Junction-to-Case Thermal

(2)

30.38

C/W

FSDL0365RN, FSDM0365RN

Electrical Characteristics

(Ta = 25

C unless otherwise specified)

Parameter Symbol

Condition

Min.

Typ.

Max.

Unit

Sense FET SECTION

Startup Voltage (Vstr) Breakdown

STR

=0V, I

=1mA

650

Drain-Source Breakdown Voltage

DSS

=0V, I

=50

A 650

Off-State Current
(Max.Rating =660V)

DSS

=660V, V

=0V -

=0.8Max.Rating,

=0V, T

=125

200

On-State Resistance

(1)

DS(ON)

=10V, I

=0.5A -

3.6

4.5

Input Capacitance

ISS

=0V, V

=25V,

F=1MHz

315

Output Capacitance

OSS

Reverse Transfer Capacitance

RSS

Turn On Delay Time

D(ON)

=325V, I

=1.0A

(Sense FET switching
time is essentially
independent of
operating temperature)

11.2 -

Rise Time

Turn Off Delay Time

D(OFF)

28.2

Fall Time

CONTROL SECTION

Output Frequency

OSC

FSDM0365R

61 67 73 KHz

Output Frequency Modulation

MOD

ą1.5 ą2.0 ą2.5 KHz

Output Frequency

OSC

FSDL0365R

45 50 55 KHz

Output Frequency Modulation

MOD

ą1.0 ą1.5 ą2.0 KHz

Frequency Change With Temperature

(2)

-25

ą5 ą10 %

Maximum Duty Cycle

MAX

Minimum Duty Cycle

MIN

Start threshold voltage

START

=GND 11

Stop threshold voltage

STOP

=GND 7

Feedback Source Current

=GND 0.7

0.9

1.1

Internal Soft Start Time

S/S

=4V 10

BURST MODE SECTION

Burst Mode Voltages

BURH

0.4 0.5 0.6 V

BURL

0.25 0.35 0.45 V

PROTECTION SECTION

Drain to Source Peak Current Limit

OVER

Max. inductor current

1.89

2.15

2.41

FSDL0365RN, FSDM0365RN

Comparison Between KA5x0365RN and FSDx0365RN

Function

KA5x0365RN

FSDx0365RN

FSDx0365RN Advantages

Soft-Start

not applicable

15mS

ˇ Gradually increasing current limit

during soft-start further reduces peak
current and voltage component
stresses

ˇ Eliminates external components used

for soft-start in most applications

ˇ Reduces or eliminates output

overshoot

External Current Limit

not applicable

Programmable of
default current limit

ˇ Smaller transformer
ˇ Allows power limiting (constant over-

load power)

ˇ Allows use of larger device for lower

losses and higher efficiency.

Frequency Modulation

not applicable

ą2.0KHz @67KHz
ą1.5KHz @50KHz

ˇ Reduced conducted EMI

Burst Mode Operation

not applicable

Yes-built into
controller

ˇ Improve light load efficiency
ˇ Reduces no-load consumption
ˇ Transformer audible noise reduction

Drain Creepage at
Package

1,02mm

7.62mm

ˇ Greater immunity to arcing as a result

of build-up of dust, debris and other
contaminants

FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Sense FET part)

-1

Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V

Note :

1. 250ľs Pulse Test
2. T

= 25

, Dr

u
r
r
ent [A]

, Drain-Source Voltage [V]

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

= 20V

= 10V

Note : T

= 25

DS(

[

r
ain

-
S

ourc

e
On-R

i
s
t
a
nc

, Drain Current [A]

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-1

150

Note :

1. V

= 0V

2. 250ľ s Pulse Test

,
Rev

e
r
s
e D

r
ain Cur

r
ent

[

]

, Source-Drain Voltage [V]

-1

100

200

300

400

500

600

700

iss

= C

+ C

= shorted)

oss

= C

+ C

rss

= C

Note ;

1. V

= 0 V

2. f = 1 MHz

rss

oss

iss

Capac

i
t
ances [

p
F]

, Drain-Source Voltage [V]

= 325V

= 130V

= 520V

Note : I

= 3.0 A

, G

a
te

-S

o
u

r
c
e V

l
t
a
ge [V

]

, Total Gate Charge [nC]

On-Resistance vs. Drain Current

Source-Drain Diode Forward Voltage

Capacitance vs. Drain-Source Voltage

Gate Charge vs. Gate-Source Voltage

Output Characteristics

FSDL0365RN, FSDM0365RN

Typical Performance Characteristics

(Continued)

-50

100

150

0.90

0.95

1.00

1.05

1.10

1.15

Note :

1. V

= 0 V

2. I

= 250 ľ A

DSS

, (No

rma

l
i
z
e
d
)

r
ai

n V

o
lt
ag

, Junction Temperature [

-50

100

150

0.5

1.0

1.5

2.0

2.5

Note :

1. V

= 10 V

2. I

= 1.5 A

(
O

,
(Nor

a
l
i
zed)

r
a
i
n-

o
ur

n
-R

i
s
t
a

n
c
e

, Junction Temperature [

Breakdown Voltage vs. Temperature

On-Resistance vs. Temperature

100

125

150

0.0

0.5

1.0

1.5

2.0

,

Dr

ain C

u
r
r
e

nt [A]

, Case Temperature [ ]

Max. Safe Operating Area

Max. Drain Current vs. Case Temperature

Thermal Response

-3

-2

-1

DC 10 s

1 s

100 ms

10 ms

1 ms

100

Operation in This Area
is Limited by R

DS(on)

, D

r
ai

r
r
e

]

, Drain-Source Voltage [V]

1E-5

1E-4

1E-3

0.01

0.1

100

1000

0.1

0.05

0.02
0.01

single pulse

0.2

0.1

D=0.5

Notes :

1. Z

(t) = 80 /W Max.

2. Duty Factor, D=t

3. T

- T

= P

* Z

(t)

(
t
)
,
Th

mal

e
spon

, Square Wave Pulse Duration [sec]

FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Control Part)

(

These characteristic graphs are normalized at Ta = 25

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

r
m

a
l
iz

Operating Frequency (Fosc)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

r
m

a
l
iz

Frequency Modulation (F

MOD

)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

r
m

a
l
i
z
ed

Maximum duty cycle (Dmax)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

r
m

i
zed

Operating supply current (Iop)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

a
lize

Start Threshold Voltage (Vstart)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50

100

150

T emp[]

r
m

a
l
iz

Stop Threshold Voltage (Vstop)

FSDL0365RN, FSDM0365RN

Functional Description

1. Startup : In previous generations of Fairchild Power
Switches (FPS) the Vstr pin had an external resistor to the
DC input voltage line. In this generation the startup resistor
is replaced by an internal high voltage current source and a
switch that shuts off when 15mS goes by after the supply
voltage, Vcc, gets above 12V. The source turns back on if
Vcc drops below 8V.

Figure 4. High voltage current source

2. Feedback Control :

The FSDx0365RN employs current

mode control, shown in figure 5. An opto-coupler (such as
the H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network. Compar-
ing the feedback voltage with the voltage across the Rsense
resistor plus an offset voltage makes it possible to control the
switching duty cycle. When the reference pin voltage of the
KA431 exceeds the internal reference voltage of 2.5V, the
H11A817A LED current increases, thus pulling down the
feedback voltage and reducing the duty cycle. This event
typically happens when the input voltage is increased or the
output load is decreased.

3. Leading edge blanking (LEB) :

At the instant the internal

Sense FET is turned on, there usually exists a high current
spike through the Sense FET, caused by the primary side
capacitance and secondary side rectifier diode reverse recov-
ery. Excessive voltage across the Rsense resistor would lead
to incorrect feedback operation in the current mode PWM
control. To counter this effect, the FPS employs a leading
edge blanking (LEB) circuit. This circuit inhibits the PWM
comparator for a short time (T

LEB

) after the Sense FET is

turned on.

Figure 5. Pulse width modulation (PWM) circuit

4. Protection Circuit :

The FPS has several protective

func-

tions such as over load protection (OLP), over voltage pro-
tection (OVP), abnormal over current protection (AOCP),
under voltage lock out (UVLO) and thermal shutdown
(TSD). Because these protection circuits are fully integrated
inside the IC without external components, the reliability is
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the FPS
resumes its normal operation. In this manner, the auto-restart
can alternately enable and disable the switching of the power
Sense FET until the fault condition is eliminated.

4.1 Over Load Protection (OLP) :

Overload is defined

as the

load current exceeding a pre-set level due to an unexpected
event. In this situation, the protection circuit should be acti-
vated in order to protect the SMPS. However, even when the
SMPS is in the normal operation, the over load protection
circuit can be activated during the load transition. In order to
avoid this undesired operation, the over load protection cir-
cuit is designed to be activated after a specified time to deter-
mine whether it is a transient situation or an overload
situation. In conjunction with the Ipk current limit pin (if
used) the current mode feedback path would limit the current
in the Sense FET when the maximum PWM duty cycle is
attained. If the output consumes more than this maximum
power, the output voltage (Vo) decreases below the set volt-
age. This reduces the current through the opto-coupler LED,
which also reduces the opto-coupler

transistor current, thus

increasing the feedback voltage (Vfb). If Vfb exceeds 3V, the feed-
back input diode is blocked and the 5uA I

delay

current source starts

to charge Cfb slowly up to Vcc. In this condition, Vfb continues
increasing until it reaches 6V, when the switching operation is ter-
minated as shown in figure 6. The delay time for shutdown is the
time required to charge Cfb from 3V to 6V with 5uA.

Vin,dc

Vstr

Vcc

15m S After UVLO

start(>12V)

off

UVLO <8V

Istr

J-FET

OSC

Vcc

Vref

2uA

0.9mA

28R

Gate

driver

OLP

Vfb*

Vfb

431

Cfb

FSDL0365RN, FSDM0365RN

Figure 6. Over load protection

4.2 Thermal Shutdown (TSD) :

The Sense FET and the

con-

trol IC are integrated, making it easier for the control IC to
detect the temperature of the Sense FET. When the tempera-
ture exceeds approximately 140

C, thermal

shutdown is acti-

vated.

4.3 Abnormal Over Current Protection (AOCP) :

Figure 7. AOCP Function & Block

Even though the FPS has OLP (Over Load Protection) and
current mode PWM feedback, these are not enough to pro-
tect the FPS when a secondary side diode short or a trans-
former pin short occurs. In addition to start-up, soft-start is
also activated at each restart attempt during auto-restart and
when restarting after latch mode is activated. The FPS has an
internal AOCP (Abnormal Over Current Protection) circuit
as shown in figure 7. When the gate turn-on signal is applied
to the power Sense FET, the AOCP block is enabled and

monitors the current through the sensing resistor. The volt-
age across the resistor is then compared with a preset AOCP
level. If the sensing resistor voltage is greater than the AOCP
level, pulse by pulse AOCP is triggered regardless of uncon-
trollable LEB time. Here, pulse by pulse AOCP stops Sense
FET within 350nS after it is activated.

4.4 Over Voltage Protection (OVP) : In case of malfunc-
tion in the secondary side feedback circuit, or feedback loop
open caused by a defect of solder, the current through the
opto-coupler transistor becomes almost zero. Then, Vfb
climbs up in a similar manner to the over load situation, forc-
ing the preset maximum current to be supplied to the SMPS
until the over load protection is activated. Because excess
energy is provided to the output, the output voltage may
exceed the rated voltage before the over load protection is
activated, resulting in the breakdown of the devices in the
secondary side. In order to prevent this situation, an over
voltage protection (OVP) circuit is employed. In general,
Vcc is proportional to the output voltage and the FPS uses
Vcc instead of directly monitoring the output voltage. If
V

exceeds 19V, OVP circuit is activated resulting in ter-

mination of the switching operation. In order to avoid undes-
ired activation of OVP during normal operation, Vcc should
be properly designed to be below 19V.

5. Soft Start :

The FPS has an internal soft start circuit

that

increases the feedback voltage together with the Sense FET
current slowly after it starts up. The typical soft start time is
15msec, as shown in figure 8, where progressive increments
of Sense FET current are allowed during the start-up phase.
The pulse width to the power switching device is progres-
sively increased to establish the correct working conditions
for transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased with the
intention of smoothly establishing the required output volt-
age. It also helps to prevent transformer saturation and
reduce the stress on the secondary diode.

Vcc

Delay current (5uA) charges the Cfb

FPS switching

OLP

Following Vcc

)

(

);

)

(

fig

delay

)

(

)

(

;

))

(

)

(

Vsense

Vfb

Out Driver

Rsense

CLK

Drain

AOCP

PWM

COMPARATOR

AOCP

COMPARATOR

LEB

1mS

15steps

Current limit

0.98A

2.15A

Drain current

[A]

FSDL0365RN, FSDM0365RN

Figure 8. Soft Start Function

6. Burst operation :

In order to minimize power

dissipation in

standby mode, the FPS enters burst mode

operation.

Figure 9. Circuit for Burst operation

As the load decreases, the feedback voltage decreases. As shown in
figure 10, the device automatically enters burst mode when the
feedback voltage drops below V

BURH

(500mV). Switching still con-

tinues but the current limit is set to a fixed limit internally to mini-
mize flux density in the transformer. The fixed current limit is
larger than that defined by Vfb = V

BURH

and therefore, Vfb is

driven down further.

Switching continues until

the feedback

voltage drops below V

BURL

(300mV). At

this point switching

stops and the output voltages start to drop at a rate dependent
on the standby current load. This causes the feedback volt-
age to rise. Once it passes

BURH

(500mV) switching resumes.

The feedback

voltage then falls and the process repeats. Burst

mode operation alternately enables and disables switching of
the power Sense FET thereby reducing switching loss in

Standby mode.

Figure 10. Circuit for Burst Operation

7. Frequency Modulation : EMI reduction can be accom-
plished by modulating the switching frequency of a switched
power supply. Frequency modulation can reduce EMI by
spreading the energy over a wider frequency range than the
band width measured by the EMI test equipment. The
amount of EMI reduction is directly related to the depth of
the reference frequency. As can be seen in Figure 11, the fre-
quency changes from 65KHz to 69KHz in 4mS for the
FSDM0265RN. Frequency modulation allows the use of a
cost effective inductor instead of an AC input mode choke to
satisfy the requirements of world wide EMI limits.

Figure 11. Frequency Modulation Waveform

D R A I N

G N D

R s e n s e

I_ o v e r

S W IT C H

O F F

5 V

Vcc

delay

2.5R

0.3/0.5V

PWM

0.5V

Vcc

B_PEAK

Burst

Normal

MOSFET

Current

0.5V

Switching OFF

Current

waveform

Burst Operation

Normal Operation

Feedback

0.3V

Burst Operation

Switching OFF

69kH z

67kH z

65kH z

4k H z

Turn-on

Turn-off

point

Internal

O scillator

D rain to

S ourc e
voltage

V ds

W aveform

D rain to

S ource
current

FSDL0365RN, FSDM0365RN

Figure 12. KA5-series FPS Full Range EMI scan(67KHz,

no Frequency Modulation) with DVD Player SET

Figure 13. FSDX-series FPS Full Range EMI Scan (67KHz,

with Frequency Modulation) with DVD Player SET

8. Adjusting Current limit function:

As shown in fig

14, a

combined 2.8K

internal resistance is connected into the

non-inverting lead on the PWM comparator. A external
resistance of Y on the current limit pin forms a parallel resis-
tance with the 2.8K

when the internal diodes are biased by

the main current source of 900uA.

Figure 14. Peak current adjustment

For example, FSDx0265RN has a typical Sense FET

current

limit (I

OVER

) of 2.15A. The Sense FET current

can be limited to

1A by inserting a 2.8k

between the current limit pin and

ground which is derived from the following equations:

2.15: 1 = 2.8K

: XK

X = 1.3K

Since X represents the resistance of the parallel network, Y
can be calculated using the following equation:

Y = X / (1 - (X/2.8K

))

Frequency (MHz)

p
litu

d
e
(d

CISPR2QB

CISPR2AB

Frequency (MHz)

p
litu

d
e
(d

CISPR2QB

CISPR2AB

PWM

comparator

SenseFET

Sense

900uA

5uA

Rsense

Feed
Back

Current

Limit

FSDL0365RN, FSDM0365RN

Typical application circuit

1. Set Top Box Example Circuit (20W Output Power)

FSDM0365RN

D D

S VccVfb

400V

/47u

UF4007

47K

UF4004

33n
50V

I_pk

start

6.8n/

1kV

30R

50V

47uF

D15

SB360

D14

D13

EGP20D

D12

PC817

FOD2741A

C11

C12

+3.3V

+5.0V

+17.0V

+23.0V

0.4~1.4A

0.2~0.85A

0.01~0.5A

0.005~0.45A

C13

C15

C17

C16

C14

1000uF

/16V

470uF

/10V

1000uF

/16V

470uF

/10V

470uF

/35V

220uF

/35V

100uF

/50V

100uF

/50V

R21

R14

R13

R15

330R

800R

6.9K

R12

2.7K

1.5K

C209

0.1uF/

monolithic

LF1

40mH

KBP06M

100pF

/400V

100pF

/400V

2A/250V

FUSE

85VAC

~275VAC

56K/1/

R19

R20

PC817

TL431AZ

EGP20D

PERFORMANCE SUMMARY
Output Power: 20W
Regulation
3.3V: ą5%
5.0V: ą5%
17.0V: ą7%
23.0: ą7%
Efficiency: 75%
No load Consumption:
0.12W at 230Vac

GreenFPS

6kR

R15

20R

R22

1KR

Figure15. 20W multiple power supply using FSDM0365RN

Multiple Output, 20W, 85-265VAC Input Power supply:
Figure 15 shows a multiple output supply typical for high
end set-top boxes containing high capacity hard disks for
recording or LIPS(LCD Inverter Power Supply) for 15"
LCD monitor. The supply delivers an output power of 20W
cont./24 W peak (thermally limited) from an input voltage of
85 to 265 VAC. Efficiency at 20W, 85VAC is

75%.

The 3.3 V and 5 V outputs are regulated to ą5% without the
need for secondary linear regulators. DC stacking (the sec-
ondary winding reference for the other output voltages is
connected to the anode of D15. For more accuracy, connec-
tion to the cathode of D15 will be better.) is used to minimize
the voltage error for the higher voltage outputs. Due to the
high ambient operating temperature requirement typical of a
set-top box (60

C) the FSDL0165RN is used to reduce con-

duction losses without a heatsink. Resistor R5 sets the device
current limit to limit overload power.

Leakage inductance clamping is provided by R1 and C8,
keeping the DRAIN voltage below 650 V under all condi-
tions. Resistor R1 and capacitor C8 are selected such that R1
dissipates power to prevent rising of DRAIN Voltage caused
by leakage inductance. The frequency modulation feature of
FSDL0165RN allows the circuit shown to meet CISPR2AB
with simple EMI filtering (C1, LF1 and C2) and the output
grounded. The secondaries are rectified and smoothed by
D12, D13, D14,and D15. Diode D15 for the 3.4V output is a
Schottky diode to maximize efficiency. Diode D14 for the 5
V output is a PN type to center the 5 V output at 5 V. The 3.3
V and 5 V output voltage require two capacitors in parallel to
meet the ripple current requirement. Switching noise filter-

ing is provided by L3, L2 and L1. Resistor R15 prevents
peak charging of the lightly loaded 23V output. The outputs
are regulated by the reference (TL431) voltage in secondary.
Both the 3.3 V and 5 V outputs are sensed via R13 and R14.
Resistor R22 provides bias for TL431and R21 sets the over-
all DC gain. Resistor R21, C209, R14 and R13 provide loop
compensation.

FSDL0365RN, FSDM0365RN

6/17/04 0.0m 001

2004 Fairchild Semiconductor Corporation

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Part Number FSDL0365RN