May 2003
2002 Fairchild Semiconductor Corporation
FDS7066N7 Rev D2 (W)
FDS7066N7
30V N-Channel PowerTrench
MOSFET
General Description
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
"low side" synchronous rectifier operation, providing an
extremely low R
DS(ON)
in a small package.
Applications
· Synchronous rectifier
· DC/DC converter
Features
· 23 A, 30 V
R
DS(ON)
= 4.5 m
@ V
GS
= 10 V
R
DS(ON)
= 5.5 m
@ V
GS
= 4.5 V
· High performance trench technology for extremely
low R
DS(ON)
· High power and current handling capability
· Fast switching
· FLMP SO-8 package: Enhanced thermal
performance in industry-standard package size
4
3
2
1
5
6
7
8
Bottom-side
Drain Contact
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source
Voltage
±16
V
I
D
Drain Current Continuous
(Note 1a)
23 A
Pulsed
60
P
D
Power Dissipation for Single Operation
(Note 1a)
3.0
(Note 1b)
1.7
W
T
J
, T
STG
Operating and Storage Junction Temperature Range
55 to +150
°C
Thermal Characteristics
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
40
°C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
0.5
°C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDS7066N7
FDS7066N7
13''
12mm
2500 units
FDS7066N7
FDS7066N7 Rev D2 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol Parameter
Test
Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
DrainSource Breakdown Voltage
V
GS
= 0 V, I
D
= 250
µA
30 V
BV
DSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
µA, Referenced to 25°C
24 mV/
°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
µA
I
GSSF
GateBody Leakage, Forward
V
GS
= 16 V, V
DS
= 0 V
100
nA
I
GSSR
GateBody Leakage, Reverse
V
GS
= 16 V, V
DS
= 0 V
100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
µA
1 1.5 3 V
V
GS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= 250
µA, Referenced to 25°C
4.3 mV/
°C
R
DS(on)
Static DrainSource
OnResistance
V
GS
= 10 V, I
D
= 23 A
V
GS
= 4.5 V, I
D
= 21 A
V
GS
= 10 V, I
D
= 23 A, T
J
= 125
°C
3.5
4.0
5.0
4.5
5.5
6.3
m
I
D(on)
OnState Drain Current
V
GS
= 10 V, V
DS
= 5 V
30
A
g
FS
Forward
Transconductance V
DS
= 10 V, I
D
= 23 A
116
S
Dynamic Characteristics
C
iss
Input
Capacitance
4973
pF
C
oss
Output
Capacitance
826
pF
C
rss
Reverse Transfer Capacitance
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
341 pF
Switching Characteristics
(Note 2)
t
d(on)
TurnOn
Delay
Time
12
22
ns
t
r
TurnOn Rise Time
8
16
ns
t
d(off)
TurnOff Delay Time
85
136
ns
t
f
TurnOff
Fall
Time
V
DD
= 15 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
25 40 ns
Q
g
Total Gate Charge
43
69
nC
Q
gs
GateSource
Charge
13
nC
Q
gd
GateDrain
Charge
V
DS
= 15 V, I
D
= 23 A,
V
GS
= 5.0 V
11 nC
DrainSource Diode Characteristics and Maximum Ratings
V
SD
DrainSource Diode Forward
Voltage
V
GS
= 0 V, I
S
= 2.5 A
(Note 2)
0.7
1.2 V
t
rr
Diode Reverse Recovery Time
34.2
nS
Q
rr
Diode Reverse Recovery Charge
I
F
= 23 A,
d
iF
/d
t
= 100 A/µs
40.4 nC
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
JC
is guaranteed by design while R
CA
is determined by the user's board design.
a) 40°C/W
when
mounted on a 1in
2
pad
of 2 oz copper
b)
85°C/W when mounted on
a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300
µs, Duty Cycle < 2.0%
FDS7066N7
FDS7066N7 Rev D2 (W)
Typical Characteristics
0
10
20
30
40
50
60
0
0.25
0.5
0.75
1
1.25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
V
GS
= 10V
2.5V
3.0V
4.5V
3.5V
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0
10
20
30
40
50
60
I
D
, DIRAIN CURRENT (A)
R
DS
(
O
N)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 3.0V
10V
3.5V
4.0V
4.5V
6.0V
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
1.8
-50
-25
0
25
50
75
100
125
150
175
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS
(
O
N)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 23A
V
GS
= 10V
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
2
4
6
8
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS
(
O
N)
, ON-RESISTANCE (OHM)
I
D
= 11.5A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation
withTemperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
10
20
30
40
50
60
1.5
2
2.5
3
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
A
= 125
o
C
25
o
C
-55
o
C
V
DS
= 5.0V
0.0001
0.001
0.01
0.1
1
10
100
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
,
BODY DIODE FORWARD VOLTAGE (V)
I
S
, REVERSE DRAIN CURRENT (A)
V
GS
= 0V
T
A
= 125
o
C
25
o
C
-55
o
C
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS7066N7
FDS7066N7 Rev D2 (W)
Typical Characteristics
0
2
4
6
8
10
0
10
20
30
40
50
60
70
80
90
Q
g
, GATE CHARGE (nC)
V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= 23A
V
DS
= 5V
10V
15V
0
800
1600
2400
3200
4000
4800
5600
6400
0
6
12
18
24
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
C
ISS
C
OSS
C
RSS
f = 1 MHz
V
GS
= 0 V
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.01
0.1
1
10
100
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
DC
1s
100ms
100
µs
R
DS(ON)
LIMIT
V
GS
= 10V
SINGLE PULSE
R
JA
= 85
o
C/W
T
A
= 25
o
C
10ms
1ms
0
10
20
30
40
50
0.01
0.1
1
10
100
t
1
, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
R
JA
= 85°C/W
T
A
= 25°C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
r(t), NO
RMALIZED EFFECTIVE
T
RANSI
E
NT
T
H
ERMAL
RESI
ST
ANCE
R
JA
(t) = r(t) + R
JA
R
JA
= 85
o
C/W
T
J
- T
A
= P * R
JA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDS7066N7
FDS7066N7 Rev D2 (W)
Dimensional Outline and Pad Layout
FDS7066N7
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