DS009793

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October 1988

Revised February 2000

DM9328

Dual

8-
Bit
Shi

f
t
Regi

DM9328
Dual 8-Bit Shift Register

General Description

The DM9328 is a high speed serial storage element provid-
ing 16 bits of storage in the form of two 8-bit registers. The
multifunctional capability of this device is provided by sev-
eral features: 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources; 2) the clock of each register may be
provided separately or together; 3) both the true and com-
plementary outputs are provided from each 8-bit register,
and both registers may be master cleared from a common
input.

Ordering Code:

Logic Symbol

Pin 16

GND

Pin 8

Connection Diagram

Pin Descriptions

Order Number

Package Number

Package Description

DM9328N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names

Description

Data Select Input

D0, D1

Data Inputs

Clock Pulse Input (Active HIGH)

Common (Pin 9)

Separate (Pins 7 and 10)

Master Reset Input (Active LOW)

Last Stage Output

Complementary Output

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9328

Functional Description

The two 8-bit shift registers have a common clock input
(pin 9) and separate clock inputs (pins 10 and 7). The
clocking of each register is controlled by the OR function of
the separate and the common clock input. Each register is
composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the R and S input. During the first LOW-to-
HIGH transition of either, or both simultaneously, of the two
clock inputs, the data inputs (R and S) are inhibited so that
a later change in input data will not affect the master; then
the now trapped information in the master is transferred to
the slave. When the transfer is complete, both the master
and the slave are steady as long as either or both clock
inputs remain HIGH. During the HIGH-to-LOW transition of
the last remaining HIGH clock input, the transfer path from
master to slave is inhibited first, leaving the slave steady in
its present state. The data inputs (R and S) are enabled so
that new data can enter the master. Either of the clock
inputs can be used as clock inhibit inputs by applying a
logic HIGH signal. Each 8-bit shift register has a 2-input

multiplexer in front of the serial data input. The two data
inputs D0 and D1 are controlled by the data select input (S)
following the Boolean expression:

Serial data in: S

SD0

SD1

An asynchronous master reset is provided which, when
activated by a LOW logic level, will clear all 16 stages inde-
pendently of any other input signal.

Shift Select Table

HIGH Voltage Level

LOW Voltage Level

Immaterial

indicates state after eight clock pulse

Logic Diagram

INPUTS

OUTPUT

Q7 (t

)

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DM9328

Absolute Maximum Ratings

(Note 1)

Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the "Electrical
Characteristics" table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.

Recommended Operating Conditions

Electrical Characteristics

Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted)

Note 2: All typicals are at V

5V, T

Note 3: Not more than one output should be shorted at a time.

Supply Voltage

Input Voltage

5.5V

Operating Free Air Temperature Range

C to

Storage Temperature Range

C to

150

Symbol

Parameter

Min

Nom

Max

Units

Supply Voltage

4.75

5.25

HIGH Level Input Voltage

LOW Level Input Voltage

0.8

HIGH Level Output Current

0.4

LOW Level Output Current

Free Air Operating Temperature

(H)

Setup Time HIGH or LOW

(L)

to CP

(H)

Hold Time HIGH or LOW

(L)

to CP

(H)

Clock Pulse Width

(L)

HIGH or LOW

(L)

MR Pulse Width with CP HIGH

(L)

MR Pulse Width with CP LOW

REC

Recovery Time MR to CP

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(Note 2)

Input Clamp Voltage

Min, I

12 mA

1.5

HIGH Level

Min, I

Max

2.4

3.4

Output Voltage

Max

LOW Level

Min, I

Max

0.2

0.4

Output Voltage

Min

Input Current @ Max Input Voltage

Max, V

5.5V

HIGH Level

Max, V

2.4V

Input Current

MR, D

Inputs

CP Inputs

S Inputs

CP (COM) Inputs

120

LOW Level

Max, V

0.4V

1.6

Input Current

MR, D

Inputs

CP Inputs

2.4

S Inputs

3.2

CP (COM) Input

4.8

Short Circuit Output Current

Max (Note 3)

Supply Current

Max

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DM9328

Dual

8-
Bit
Shi

f
t
Regi

Physical Dimensions

inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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Part Number DM9328