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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
·
(510) 668-7000
·
FAX (510) 668-7017
·
www.exar.com
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JUNE 2003
REV. 1.0.0
GENERAL DESCRIPTION
The XRT75L03D is a three-channel fully integrated
Line Interface Unit (LIU) with Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates 3
independent Receivers, Transmitters and Jitter
Attenuators in a single 128 pin LQFP package.
Each channel of the XRT75L03D can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75L03D's differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75L03D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L03D supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
RECEIVER:
·
On chip Clock and Data Recovery circuit for high
input jitter tolerance
·
Meets E3/DS3/STS-1 Jitter Tolerance Requirement
·
Detects and Clears LOS as per G.775
·
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
·
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
·
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
·
Provides low jitter output clock
TRANSMITTER:
·
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
·
Tri-state Transmit output capability for redundancy
applications
·
Each Transmitter can be turned on or off
·
Transmitters provide Current Drive Output
JITTER ATTENUATOR:
·
On chip advanced crystal-less Jitter Attenuator for
each channel
·
Jitter Attenuator can be selected in Receive or
Transmit paths
·
Meets ETSI TBR 24 Jitter Transfer Requirements
·
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
·
Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
·
5 wire Serial Microprocessor Interface for control
and configuration
·
Supports optional internal Transmit driver
monitoring
·
Hardware Mode for control and configuration
·
Each channel supports Local, Remote and Digital
Loop-backs
·
Single 3.3 V ± 5% power supply
·
5 V Tolerant I/O
·
Available in 128 pin Thermally enhanced LQFP
Package
·
- 40°C to 85°C Industrial Temperature Range
APPLICATIONS
·
E3/DS3 Access Equipment
·
STS1-SPE to DS3 De-Synchronizing
·
DSLAMs
·
Digital Cross Connect Systems
·
CSU/DSU Equipment
·
Routers
·
Fiber Optic Terminals
XRT75L03D
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REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
TRANSMIT INTERFACE CHARACTERISTICS
·
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
·
Integrated Pulse Shaping Circuit
·
Built-in B3ZS/HDB3 Encoder (which can be disabled)
·
Accepts Transmit Clock with duty cycle of 30%-70%
·
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications
·
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499
-CORE
and
ANSI T1.102_1993
·
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE
·
Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
·
Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery
·
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications
·
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications
·
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications
·
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms
·
Built-in B3ZS/HDB3 Decoder (which can be disabled)
·
Recovered Data can be muted while the LOS Condition is declared
·
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L03D
H O S T /H W
S T S -1/D S 3 _(n )
E 3 _(n )
R E Q E N _(n )
R T IP _(n )
R R in g _(n )
S R /D R
X R T 7 5 L 0 3 D
R L B _(n )
R L O S _(n )
JA T x/R x
T P D a ta_ (n)
T N D ata_ (n )
T xC lk_ (n )
T AO S _(n )
T xL E V _ (n )
T xO N _(n )
C h an n el 2
C h an n el 0
C h an n el 1
N o te s: 1. (n ) = 0, 1 o r 2 fo r resp ec tive C h an n els
2. S eria l P ro ce s so r In terface in p u t p in s a re sh a re d b y th e th ree C h an n els in " H o s t" M o d e an d red efin ed in th e "H a rd w a re" M o d e.
D evice
M o nitor
M T IP _(n)
M R in g_ (n )
D M O _(n )
Tim in g
C on tro l
T T IP _(n )
T R in g_ (n )
Tx
Pu lse
Sh apin g
HDB 3/
B3 ZS
En co der
R L O L _(n )
R xO N
R xC lkIN V
R xC lk_ (n )
R P O S _(n )
R N E G _ (n)/
L C V _ (n )
Tx
C on trol
Jitter
A tte nua to r
M U X
Line
Driver
L O S T H R
L L B _(n )
Invert
Rem o te
Lo opB ack
HDB 3/
B3 ZS
D ecod er
M U X
AG C/
Eq ualizer
Pe ak Detector
LO S
Detector
Slice r
Jitter
Attenu ator
Se rial
Proce ssor
Inte rfa ce
Lo cal
Lo op Ba ck
C lock & D a ta
R ec overy
C lock
S ynthe sizer
E 3 C lk,D S 3 C lk,
S T S -1C lk
R E S E T
C S
S C lk
IN T
S D O
S D I
C L K O U T
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.0
3
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75L03D
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT75L03DIV
128 Pin LQFP
- 40
°
C to + 85
°
C
R L O L _ 2
R L O S _ 2
IC T
R L O L _ 0
R L O S _ 0
R x D G N D _ 0
R P O S _ 0
R N E G _ 0 /L C V _ 0
R x C lk _ 0
R x D V D D _ 0
R x D V D D _ 2
R P O S _ 2
R N E G _ 2 /L C V _ 2
R x C lk _ 2
R x D G N D _ 2
A G N D _ 0
J A G N D _ 2
J A G N D _ 0
J A V D D _ 0
J A V D D _ 2
J A 0
J A T x /R x
J A 1
T x A G N D _ 0
D M O _ 0
T x A V D D _ 0
Tx
O
N
_
1
T
NDa
t
a
_
1
T
P
D
a
t
a_1
Tx
C
l
k
_
1
MR
i
n
g
_
1
MT
I
P
_
1
TA
O
S
_
1
TA
O
S
_
2
T
x
L
EV_
1
T
x
L
EV_
2
TTI
P
_
1
Tx
V
D
D
_
1
TR
i
n
g
_
1
T
x
G
ND_
1
Tx
A
G
N
D
_
2
MR
i
n
g
_
2
MT
I
P
_
2
T
x
G
ND_
2
TR
i
n
g
_
2
Tx
V
D
D
_
2
TTI
P
_
2
DM
O
_
2
Tx
A
V
D
D
_
2
T
NDa
t
a
_
2
T
P
D
a
t
a_2
Tx
C
l
k
_
2
T
x
G
ND_
0
TR
i
n
g
_
0
Tx
V
D
D
_
0
TTI
P
_
0
MT
I
P
_
0
MR
i
n
g
_
0
T
NDa
t
a
_
0
T
P
D
a
t
a_0
Tx
C
l
k
_
0
T
x
L
EV_
0
TA
O
S
_
0
Tx
O
N
_
0
R L O L _ 1
R L O S _ 1
E X D G N D
S F M _ E N
E 3 C lk /C L K _ E N
D S 3 C lk /C L K _ O U T
S T S -1 C lk /1 2 M
E X D V D D
R x D V D D _ 1
R P O S _ 1
R N E G _ 1 /L C V _ 1
R x C lk _ 1
R x D G N D _ 1
A G N D _ 1
J A D G N D
J A G N D _ 1
J A D V D D
J A V D D _ 1
R E F A V D D
R X A
R X B
R E F G N D
T x O N _ 2
T x A G N D _ 1
D M O _ 1
T x A V D D _ 1
X R T 7 5 L 0 3 D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1 0 3
1 0 4
1 0 5
1 0 6
1 0 7
1 0 8
1 0 9
1 1 0
1 1 1
1 1 2
1 1 3
1 1 4
1 1 5
1 1 6
1 1 7
1 1 8
1 1 9
1 2 0
1 2 1
1 2 2
1 2 3
1 2 4
1 2 5
1 2 6
1 2 7
1 2 8
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
TE
S
T
R
ESE
T
A
G
ND_
2
LO
S
T
H
R
ST
S
-
1
/
D
S
3
_
1
LL
B
_
1
RL
B
_
1
RE
Q
E
N_
1
E
3_1
Rx
A
V
D
D
_
1
R
R
i
ng
_1
RT
I
P
_
1
Rx
A
G
ND_
1
Rx
A
G
ND_
2
RT
I
P
_
2
R
R
i
ng
_2
Rx
A
V
D
D
_
2
E
3_2
RE
Q
E
N_
2
RL
B
_
2
LL
B
_
2
ST
S
-
1
/
D
S
3
_
2
Rx
A
G
ND_
0
RT
I
P
_
0
R
R
i
ng
_0
Rx
A
V
D
D
_
0
E
3_0
RE
Q
E
N_
0
RL
B
_
0
LL
B
_
0
ST
S
-
1
/
D
S
3
_
0
L
O
S
M
U
T
/IN
T
HO
S
T
/
H
W
Rx
M
O
N/
S
D
O
Rx
O
N
/
S
D
I
T
x
Cl
k
I
NV
/
S
Cl
k
Rx
Cl
k
I
NV
/
C
S
SR
/
D
R
XRT75L03D
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REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
I
GENERAL DESCRIPTION ............................................................................................... 1
F
EATURES
.................................................................................................................................................... 1
A
PPLICATIONS
.............................................................................................................................................. 1
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
...................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................ 2
Figure 1. Block Diagram of the XRT 75L03D .................................................................................................... 2
Figure 2. Pin Out of the XRT75L03D ................................................................................................................ 3
ORDERING INFORMATION ................................................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
S
YSTEM
-S
IDE
T
RANSMIT
I
NPUT
AND
T
RANSMIT
C
ONTROL
P
INS
...................................................................... 4
T
RANSMIT
L
INE
S
IDE
P
INS
............................................................................................................................ 8
S
YSTEM
-S
IDE
R
ECEIVE
O
UTPUT
AND
R
ECEIVE
C
ONTROL
P
INS
.................................................................... 10
R
ECEIVE
L
INE
S
IDE
P
INS
............................................................................................................................ 17
C
LOCK
I
NTERFACE
...................................................................................................................................... 18
G
ENERAL
C
ONTROL
P
INS
........................................................................................................................... 19
C
ONTROL
AND
A
LARM
I
NTERFACE
............................................................................................................... 21
J
ITTER
A
TTENUATOR
INTERFACE
................................................................................................................. 21
P
OWER
S
UPPLY
AND
G
ROUND
P
INS
............................................................................................................ 24
XRT75L03D P
IN
L
ISTING
IN
N
UMERICAL
O
RDER
......................................................................................... 26
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 31
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................ 31
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
: ................................................................................................... 31
2.0 TIMING CHARACTERISTICS ............................................................................................................ 32
Figure 3. Typical interface between terminal equipment and the XRT75L03D (dual-rail data) ....................... 32
Figure 4. Transmitter Terminal Input Timing ................................................................................................... 32
Figure 5. Receiver Data output and code violation timing .............................................................................. 33
Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 33
3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 34
3.1 E3
LINE
SIDE
PARAMETERS
: ............................................................................................................................. 34
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... 34
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
........................... 35
Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ 36
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................ 36
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) . 37
Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 .................................................. 38
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................... 38
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ..... 39
Figure 10. Microprocessor Serial Interface Structure ...................................................................................... 39
Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................ 40
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F) ..... 40
FUNCTIONAL DESCRIPTION: ........................................................................................ 41
4.0 The Transmitter Section: ................................................................................................................. 41
Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 41
Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 41
4.1 T
RANSMIT
C
LOCK
: ........................................................................................................................................... 42
4.2 B3ZS/HDB3 E
NCODER
: .................................................................................................................................. 42
4.2.1 B3ZS Encoding: ................................................................................................................................. 42
4.2.2 HDB3 Encoding: ................................................................................................................................. 42
Figure 14. B3ZS Encoding Format ................................................................................................................. 42
Figure 15. HDB3 Encoding Format ................................................................................................................. 42
4.3 T
RANSMIT
P
ULSE
S
HAPER
: .............................................................................................................................. 43
4.3.1 Guidelines for using Transmit Build Out Circuit: ............................................................................ 43
4.3.2 Interfacing to the line: ........................................................................................................................ 43
4.4 T
RANSMIT
D
RIVE
M
ONITOR
: ............................................................................................................................. 44
4.5 T
RANSMITTER
S
ECTION
O
N
/O
FF
: ...................................................................................................................... 44
5.0 The Receiver Section: ...................................................................................................................... 44
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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.0
II
5.1 AGC/E
QUALIZER
: ............................................................................................................................................ 44
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 44
5.1.1 Interference Tolerance: ..................................................................................................................... 45
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45
5.2 C
LOCK
AND
D
ATA
R
ECOVERY
: ......................................................................................................................... 46
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 46
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 46
5.3 B3ZS/HDB3 D
ECODER
: .................................................................................................................................. 47
5.4 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
: ................................................................................................................ 47
5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47
D
ISABLING
ALOS/DLOS D
ETECTION
: ......................................................................................................... 47
5.4.2 E3 LOS Condition: ............................................................................................................................. 47
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 47
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49
6.0 Jitter: ................................................................................................................................................. 49
6.1 J
ITTER
T
OLERANCE
- R
ECEIVER
: ...................................................................................................................... 49
6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 49
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 50
6.2 J
ITTER
T
RANSFER
- R
ECEIVER
/T
RANSMITTER
: .................................................................................................. 51
6.3 J
ITTER
A
TTENUATOR
: ...................................................................................................................................... 51
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ..................................... 51
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................... 51
6.3.1 Jitter Generation: ............................................................................................................................... 52
7.0 Serial Host interface: ....................................................................................................................... 52
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 52
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
............................................................................................................ 53
T
ABLE
15: XRT75L03D R
EGISTER
M
AP
- Q
UICK
L
OOK
..................................................................................... 54
................................................................................................................................................................. 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU IC ..
56
Legend: .................................................................................................................................................................. 56
T
ABLE
16: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75L03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 56
THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58
................................................................................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
.................................................................... 58
T
ABLE
18: APS/R
EDUNDANCY
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00) .................................. 58
T
ABLE
19: B
LOCK
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR32 (A
DDRESS
L
OCATION
= 0
X
20) ......................... 61
T
ABLE
20: B
LOCK
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR33 (A
DDRESS
L
OCATION
= 0
X
21) ......................... 62
T
ABLE
21: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR62 (A
DDRESS
L
OCATION
= 0
X
3E) .......................................... 63
................................................................................................................................................................. 64
THE PER-CHANNEL REGISTERS ......................................................................................................... 64
T
ABLE
22: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR63 (A
DDRESS
L
OCATION
= 0
X
3F) ........................................ 64
T
ABLE
23: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75L03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66
T
ABLE
24: S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
01 ................. 66
T
ABLE
25: S
OURCE
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
02 ................. 68
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