EXAR Corporation, 48720 Kato Road, Fremont, CA 94538

(510) 668-7000

FAX (510) 668-7017

XRD9855/L55

CCD Image Digitizers with

CDS, PGA and 10-Bit A/D

December 1998-2

FEATURES

10-Bit Resolution ADC

Up to 25MHz Sampling Rate

Correlated Double Sampling (CDS)

Programmable Gain from 6dB to 38dB (PGA)

Digital Offset-Calibration

CCD Black Level Offset Compensation

CDS Clocks Sample Rising Edge or Falling Edge

Single 5V or 3V Power Supply

Low Power for Battery Applications:

XRD9855: 250mW @ V

= 5.0V

XRD98L55: 120mW @ V

= 3.0V

A-Typ Current in Stand By Mode

3-State Digital Outputs

ESD Protection to Over 2000V

APPLICATIONS

Digital Video Camcorders

Digital Still Cameras

PC Video Teleconferencing

Digital Copiers

Infrared Image Digitizers

CCD/CIS Imager Interface

GENERAL DESCRIPTION

The XRD9855/XRD98L55 are complete CCD Image
Digitizers for digital cameras. The products include a
high bandwidth differential Correlated Double Sampler
(CDS), 8-bit digitally Programmable Gain Amplifier
(PGA), 10-bit Analog-to-Digital Converter (ADC) and
digital black level auto-calibration circuitry.

The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode signal noise and power supply noise are
rejected by the differential CDS input stage. CDS inputs
are designed to be used either differential or single-
ended.

The auto calibration circuit compensates for any inter-
nal offset of the XRD9855/XRD98L55 as well as black
level offset from the CCD.

The PGA is digitally controlled with 8-bit resolution on
a linear dB scale, resulting in a gain range of 6dB to
38dB with 0.125dB per LSB of the gain code.

The PGA and black level auto-calibration are controlled
through a simple 3-wire serial interface. The timing
circuitry is designed to enable users to select a wide
variety of available CCD and image sensors for their
applications.

The XRD9855/XRD98L55 has direct access to the
PGA output and ADC input through the pin TESTVIN.

The XRD9855/XRD98L55 are packaged in 48-lead
surface mount TQFP to reduce space and weight, and
suitable for hand-held and portable applications.

ORDERING INFORMATION

Operating

Part No.

Package

Temperature Range

Power Supply

XRD9855AIV

48 Lead TQFP (7 x 7 x 1.0 mm)

-40

C to 85

5.0V

XRD98L55AIV

48 Lead TQFP (7 x 7 x 1.0 mm)

-40

C to 85

3.0V

Preliminary

XRD9855/L55

Rev. 1.00

Preliminary

PIN CONFIGURATION

48 Lead TQFP (7 x 7 x 1.0 mm)

PIN DESCRIPTION 48 pin TQFP

Pin #

Symbol

Description

No Connect.

DB2

ADC Output. DB0 is the LSB, DB9 is the MSB.

DB3

ADC Output.

DB4

ADC Output.

DGND

Digital Output Ground.

Digital Output Power Supply. Must be less than or equal to V

DB5

ADC Output.

DB6

ADC Output.

DB7

ADC Output.

No Connect.

DB8

ADC Output.

DB9

ADC Output. MSB

OVER

Over Range Output Bit. OVER goes high to indicate the ADC input voltage is
greater than V

CLAMP

SHD

SHP

RSTCCD

GND

CLK_POL

SYNC

UNDER

DB0
DB1

DB8

DB9

OVER

EnableCal

GND

Test

STBY1

STBY2

RESET

SCLK

DB2

DB3

DB4

DGND

DB5

DB6

DB7

LOAD

SDI

RTO

In_Neg

In_Pos

GND

RBO

XRD9855/L55

Rev. 1.00

Preliminary

PIN DESCRIPTION 48 pin TQFP (CONT'D)

Pin #

Symbol

Description

Digital Output Enable (Three-State Control). Pull OE low to enable output
drivers. Pull OE high to put output drivers in high impedance state.

Analog Power Supply.

EnableCal

Calibration Enable. Automatic offset calibration control.

GND

Analog Ground.

TESTVIN

ADC Test Input & PGA Test Output.

STBY1

Standby Control 1. Pull low to put chip in power down mode.

STBY2

Standby Control 2. Short to STBY1 pin if not using TESTVIN pin.

RESET

Chip Reset. Pull high to reset all internal registers.

SCLK

Shift Clock. Shift register latches SDI data on rising edges of SCLK.

No Connect.

LOAD

Data Load. Rising edge loads data from shift register to internal register. Load
must be low to enable shift register.

SDI

Serial Data Input.

Top ADC Reference. Voltage at V

sets full-scale of ADC.

RTO

Internal Bias for V

. Short V

to V

RTO

to use internal reference voltage.

Analog Power Supply.

In_Neg

CDS Inverting Input. Connect via capacitor to CCD video output.

In_Pos

CDS Non-inverting Input. Connect via capacitor to CCD supply.

GND

Analog Ground.

RBO

Internal Bias for V

RB.

Short V

to V

RB0

to use internal reference voltage.

Bottom ADC Reference. Voltage at V

sets zero scale of the ADC.

No Connect.

CLAMP

CDS DC Restore Clamp. Clamps In_Pos & In_Neg to internal bias voltage.

SHD

CDS Clock. Controls sampling of the pixel video level.

SHP

CDS Clock. Controls sampling of the pixel black level.

RSTCCD

CCD Reset Pulse Disconnect. Used to decouple CDS during the reset pulse.

GND

Analog Ground.

CLK_POL

Clock Polarity. Controls the polarity of SHP, SHD & CLAMP.

Analog Power Supply.

SYNC

Digital output for Exar test purposes only. No connect.

UNDER

Under Range Output Bit. UNDER goes high to indicate the ADC input voltage
is less than V

DBO

ADC Output. LSB

DB1

ADC Output.

No Connect.

XRD9855/L55

Rev. 1.00

Preliminary

DC ELECTRICAL CHARACTERISTICS XRD9855
Unless otherwise specified: DV

= V

= 5.0V, Pixel Rate = 18MSPS, V

= 3.8V, V

= 0.5V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

CDS Performance

CDSV

Input Range

200

800

Pixel (Black Level - Video Level)

Small Signal Bandwidth (-3dB)

MHz

Slew Rate

V/ľs

400mV Step Input.

Feedthrough (Hold Mode)

-60

PGA Parameters

MIN

Minimum Gain

MAX

Maximum Gain

PGA n

Resolution

bits

Transfer function is linear steps in dB
(1LSB = 0.125dB).

Gain Error

% FS

At maximum or minimum gain
setting.

ADC Parameters (Measured Through TESTVIN)

ADC n

Resolution

bits

Max Sample Rate

MSPS

DNL

Differential Non-Linearity

+0.75

LSB

Up to 18MHz sample rate.

DNL25

Differential Non-Linearity

+0.9

LSB

Up to 25MHz sample rate.

EZS

Zero Scale Error

-5

Measured relative to V

EFS

Full Scale Error

% FS

DC Input Range

GND

of the ADC can swing from GND

to V

. Input range is limited by

the output swing of the PGA.

Top Reference Voltage

1.3

3.8

Bottom Reference Voltage

0.3

0.5

-1

REF

Differential Reference Voltage

1.0

3.3

Ladder Resistance

500

Ohms

Self Bias V

0.5

connected to V

RBO.

Self Bias V

3.8

connected to V

RTO.

(

= V

)

(

= V

1.30

)

XRD9855/L55

Rev. 1.00

Preliminary

DC ELECTRICAL CHARACTERISTICS XRD9855 (CONT'D)
Unless otherwise specified: DV

= V

= 5.0V, Pixel Rate = 18MSPS, V

= 3.8V, V

= 0.5V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

System Specifications

DNL

SMIN

DNL @ Minimum Gain

0.75

LSB

DNL

SMAX

DNL @ Maximum Gain

0.75

LSB

INL

SMIN

INL @ Minimum Gain

LSB

INL error is dominated by CDS/PGA
linearity.

INL

SMAX

INL @ Maximum Gain

LSB

INL error is dominated by CDS/PGA
linearity.

OS MINAV

Offset (Input Referred) @

Offset is defined as the input pixel

Minimum Gain

value-0.5 LSB required to cause the
ADC output to switch from "Zero
scale" to "Zero scale + 1LSB".

Offset is measured after calibration.

OS MAXAV

Offset (Input Referred) @

Zero scale is the code in the offset

Maximum Gain

Offset depends on PGA gain code.

MAXAV

Input Referred Noise @

0.2

rms

Noise depends upon gain setting of

Maximum Gain

the PGA.

MINAV

Input Referred Noise @

3.5

rms

Noise depends upon gain setting of

Minimum Gain

the PGA.

Digital Inputs

Digital Input High Voltage

2.0

Digital Input Low Voltage

0.7

DC Leakage Current

Input Between GND and V

DD.

Input Capacitance

Digital Outputs

Digital Output High Voltage

-0.5

While sourcing 2mA.

Digital Output Low Voltage

0.5

While sinking 2mA.

High-Z Leakage

-10

OE=1 or STBY1= STBY2 = 0.
Output between GND & DV

DD.

XRD9855/L55

Rev. 1.00

Preliminary

DC ELECTRICAL CHARACTERISTICS XRD9855
Unless otherwise specified: DV

= V

= 5.0V, Pixel Rate = 18MSPS, V

= 3.8V, V

= 0.5V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

Digital I/O Timing

Data Valid Delay

PW1

Pulse Width of SHD

PW2

Pulse Width of SHD

PIX

Pixel Period

Sample Black Aperture Delay

= 4.5V to 5.5V,

Temperature -40°C to 85°C range

Sample Video Aperture Delay

= 4.5V to 5.5V,

Temperature -40°C to 85°C range

RST

RSTCCD Switch Delay

= 4.5V to 5.5V,

Temperature -40°C to 85°C range

Shift Clock Period

100

SET

Shift Register Setup Time

Latency

Pipeline Delay

cycles

Power Supplies

Analog Supply Voltage

4.5

5.0

5.5

Digital Output Supply Voltage

2.7

5.0

5.5

< V

Always

Supply Current

= 5.0V

DD25

Supply Current @ 25MHz

= 25MHz

DDPD

Power Down Supply Current

100

STBY1 = 0 and STBY2 = 0

XRD9855/L55

Rev. 1.00

Preliminary

DC ELECTRICAL CHARACTERISTICS XRD98L55
Unless otherwise specified: DV

= V

= 2.7V, Pixel Rate = 18MSPS, V

= 2.07V, V

= 0.27V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

CDS Performance

CDSV

Input Range

200

800

Pixel (Black Level - Video Level)

Small Signal Bandwidth (-3dB)

MHz

Slew Rate

V/ľs

400mV Step Input.

Feed-through (Hold Mode)

-60

PGA Parameters

MIN

Minimum Gain

MAX

Maximum Gain

PGA n

Resolution

bits

Transfer function is linear steps in dB
(1LSB = 0.125dB).

Gain Error

% FS

At maximum or minimum gain
setting.

ADC Parameters (Measured Through TESTVIN)

ADC n

Resolution

bits

Max Sample Rate

MSPS

DNL

Differential Non-Linearity

+0.75

LSB

Up to 18MHz sample rate.

DNL25

Differential Non-Linearity

+0.9

LSB

Up to 25MHz sample rate.

EZS

Zero Scale Error

-5

Measured relative to V

EFS

Full Scale Error

% FS

DC Input Range

GND

of the ADC can swing from GND to

. Input range is limited by

the output swing of the PGA.

Top Reference Voltage

1.2

2.07

Bottom Reference Voltage

0.2

0.27 V

-1

REF

Differential Reference Voltage

1.0

1.8

Ladder Resistance

500

Ohms

Self Bias V

0.27

connected to V

RBO.

Self Bias V

2.07

connected to V

RTO.

(

= V

)

(

= V

1.30

)

XRD9855/L55

Rev. 1.00

Preliminary

DC ELECTRICAL CHARACTERISTICS XRD98L55 (CONT'D)
Unless otherwise specified: DV

= V

= 2.7V, Pixel Rate = 18MSPS, V

= 2.7V, V

= 0.27V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

System Specifications

DNL

SMIN

DNL @ Minimum Gain

0.75

LSB

DNL

SMAX

DNL @ Maximum Gain

0.75

LSB

INL

SMIN

INL @ Minimum Gain

LSB

INL error is dominated by CDS/PGA
linearity.

INL

SMAX

INL @ Maximum Gain

LSB

INL error is dominated by CDS/PGA
linearity.

OS MINAV

Offset (Input Referred) @

Offset is defined as the input pixel

Minimum Gain

value -0.5 LSB required to cause the
ADC output to switch from "Zero
scale" to "Zero scale + 1LSB".

Offset is measured after
calibration.

OS MAXAV

Offset (Input Referred) @

Zero scale is the code in the offset

Maximum Gain

Offset depends on PGA gain code.

MAXAV

Input Referred Noise @

0.2

rms

Noise depends upon gain setting of

Maximum Gain

the PGA.

MINAV

Input Referred Noise @

3.5

rms

Noise depends upon gain setting of

Minimum Gain

the PGA.

Digital Inputs

Digital Input High Voltage

1.5

Digital Input Low Voltage

0.7

DC Leakage Current

Input Between GND and V

DD.

Input Capacitance

Digital Outputs

Digital Output High Voltage

-0.5

While sourcing 2mA.

Digital Output Low Voltage

0.5

While sinking 2mA.

HighZ Leakage

-10

OE=1 or STBY1= STBY2 = 0.
Output between GND & DV

DD.

XRD9855/L55

Rev. 1.00

Preliminary

ABSOLUTE MAXIMUM RATINGS (T

= +25

C unless otherwise noted)

1, 2, 3

to GND

+7.0V

& V

+0.5 to GND -0.5V

All Inputs

+0.5 to GND -0.5V

All Outputs

+0.5 to GND -0.5V

Storage Temperature

-65

C to 150

Lead Temperature (Soldering 10 seconds)

300

Maximum Junction Temperature

150

Package Power Dissipation Ratings (T

= +70

TQFP

= 54

C/W

ESD

2000V

Notes:

Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode
clamps (HP50822835) from input pin to the supplies. All inputs have protection diodes which will protect the
device from short transients outside the supplies of less than 100mA for less than 100ľs.

refers to AV

and DV

. GND refers to AGND and DGND.

DC ELECTRICAL CHARACTERISTICS XRD98L55 (CONT'D)
Unless otherwise specified: DV

= V

= 2.7V, Pixel Rate = 18MSPS, V

= 2.07V, V

= 0.27V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

Digital I/O Timing

Data Valid Delay

PW1

Pulse Width of SHD

PW2

Pulse Width of SHD

PIX

Pixel Period

Sample Black Aperture Delay

= 2.7V to 3.6V,

Temperature -40°C to 85°C range

Sample Video Aperture Delay

= 2.7V to 3.6V,

Temperature -40°C to 85°C range

RST

RSTCCD Switch Delay

= 2.7V to 3.6V,

Temperature -40°C to 85°C range

Shift Clock Period

100

SET

Shift Register Setup Time

Latency

Pipeline Delay

cycles

Power Supplies

Analog Supply Voltage

2.7

3.0

3.6

Digital Output Supply Voltage

2.7

3.0

3.6

< V

Always

Supply Current

= 3.0 V

DD25

Supply Current @ 25MHz

= 25MHz

DDPD

Power Down Supply Current

100

STBY1 = 0 and STBY2 = 0

XRD9855/L55

Rev. 1.00

Preliminary

SYSTEM DESCRIPTION

Correlated Double Sample/Hold (CDS) &
Programmable Gain Amplifier (PGA); Gain [7:0]

The function of the CDS block, shown in

Figure 2, is to

sense the voltage difference between the black level
and video level for each pixel. The CDS and PGA are
fully differential. The PGA output is converted to a
single ended signal, and then fed to the ADC. IN_POS
(CDS non-inverting input) should be connected, via a
capacitor, to the CCD "Common" voltage. This is
typically VCC of the CCD, but could also be the CCD
Reference output or ground. IN_NEG (CDS inverting
input) should be connected, via a capacitor, to the CCD
output signal.

During the black reference phase of each pixel the
SDRK switches are turned on, shorting the PGA1
inputs to V

. The sampling edge of SHP turns off the

SDRK switches, sampling the black reference voltage
on capacitors C1 & C2.

During the video phase of each pixel the SPIX switches
are turned on. The difference between the pixel refer-
ence level and video level is transmitted through ca-
pacitors C1 & C2 and converted to a fully differential
signal by the differential amplifier PGA1. The sampling
edge of SHD turns off the SPIX switches, sampling the
pixel value on capacitors C3 & C4.

Figure 2. Block Diagram of the CDS & PGA

PGA1

VBIAS~0.8

External

Coupling

Capacitors

CCD

Signal

CCD

Supply

CLAMP

SDRK

In_Pos

In_Neg

PGA2

BUF

SPIX

Gain

ADC

XRD9855/XRD98L55

RSTCCD

Offset

Calibration

Enable Cal

Code

ADC

CDS

PGA

XRD9855/L55

Rev. 1.00

Preliminary

RSTCCD

SHP

CCD

SHD

SDRK

SPIX

ADCLK

PGA1

Output

(Internal Signals)

Hold

Track

PGA2

Output

Figure 3. Timing Diagram of the CDS Clocks

and Internal Signals, CLK_POL = 1, M2 = 0

PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x,
and 6.25x). The gain transitions occur at PGA gain
codes 64d and 128d (40h & 80h). PGA2 provides gain
from 6dB to 22dB (2x to 12.5x) with 0.125dB steps.
Figure 4 shows the measured PGA gain vs. Gain
Code. The combined PGA blocks provide a program-
mable gain range of 32dB. The minimum gain (code
00h) is 6dB ą 1dB. The maximum gain (code FFh) is
38dB ą 1dB. The following equation can be used to
compute PGA gain from the gain code:

Gain dB

code

[

]

= +

256

where code is between 0 and 255.
Due to device mismatch the gain steps at codes 63-
64 and 127-128 may not be monotonic. The maxi-
mum error is within 0.25dB.

128

192

256

Gain Code

PGA Gain [dB]

= 25

= 18MHz

= 3.0V

= 2.3V

= 0.3V

Figure 4. PGA Gain vs. Gain Code

XRD9855/L55

Rev. 1.00

Preliminary

Analog-to-Digital Converter

The analog-to-digital converter is based upon a two-
step sub-ranging flash converter architecture with a
built in track and hold input stage. The ADC conversion
is controlled by an internally generated signal, ADCLK
(see

Figure 3). The ADC tracks the output of the CDS/

PGA while ADCLK is high and holds when ADCLK is
low. This allows maximum time for the CDS/PGA
output to settle to its final value before being sampled.
The conversion is then performed and the parallel
output is updated, after a 2.5 cycle pipeline delay, on
the rising edge of RSTCCD. The pipeline delay of the
entire XRD9855/XRD98L55 is 4 clock cycles. The
references of the ADC can be generated internally or
external voltages can be applied.

The internal reference values are set by a resistor
divider between V

and GND. To enable the internal

reference, connect V

RTO

to V

and connect V

RBO

. To maximize the performance of the XRD9855/

XRD98L55, the internal references should be used and
decoupled to GND. Although the internal references
have been set to maximize the performance of the
CDS/PGA channel, some applications may require
other reference values. To use external references,
drive the V

and V

pins directly with the desired

voltages, and leave V

RBO

and V

RTO

open (NC). The

ADC parallel output bus is equipped with a high imped-
ance capability, controlled by OE. The outputs are
enabled when OE is low.

Automatic Offset Calibration, Offset [7:0]

To get the maximum color resolution and dynamic
range, this part uses a digital offset calibration system
to compensate for external offset in the CCD signal as
well as internal offsets of the CDS, PGA and ADC.

The calibration is performed every line when the CCD
outputs the Optical Black pixels, please see the
section on Line Timing. The Calibration logic com-
pares the ADC output to the value stored in the serial
port offset register, and increments or decrements the
offset adjust DAC to make the ADC code equal to the
code in the offset register. On every line, the first
adjustment requires 8 pixels, then 6 pixels for subse-
quent adjustments. The offset register is 8 bits wide.
Two MSBs set to 00 are added when compared to the
10-bit ADC code. After power-up the part may require
up to 264 adjustments to converge on the proper offset.
These adjustments can be made over many lines. For
example, with 20 optical black pixels per line, the
calibration will make 3 adjustments per line, and initial
convergence will require at most 88 lines.

100

150

200

250

PGA Gain Setting (code)

Calibration Range (mV)

Graph 1. XRD9855 Typical Vdrk (CCD Offset)

Calibration Range

XRD9855/L55

Rev. 1.00

Preliminary

CDS

ADC

Offset Adjust

DAC

PGA

DB[9:0]

XOE

ADCLOCK

Offset Reg

State

Machine

EnableCal

IN_POS

IN_NEG

Reg

Enable

Reg

A-B

Up/Down

Counter

Figure 5. Automatic Offset Calibration Loop

Figure 6. Manual Global Offset & Automatic

Offset Calibration

Serial Interface

A three wire serial interface, (LOAD, SCLK, and SDI),
is used to program the PGA gain register, the Calibra-
tion offset register, the Mode control register, and the
Aperture delay register. The shift register is 10 bits
long. The first two bits loaded are the address bits that
determine which of the four registers to update. The
following eight bits are the data bits (MSB first, LSB
last). When LOAD is high SCLK is internally disabled.
Since SCLK is gated by LOAD, SCLK can be a
continuously running clock signal, but this will increase
system noise. To enable the shift register the LOAD pin
must be pulled low. The data at SDI is strobed into the
shift register on the rising edges of SCLK. When the
LOAD signal goes high the data bits will be written to the
register selected by the address bits (see

Figure 7).

Manual Global Offset, V [1:0]

In some systems the black level offset can be larger
than the Automatic Offset Calibration Range. The
XRD9855 provides a user programmable global offset
adjustment which adds to the automatic offset calibra-
tion. The global offset is applied at the CDS input, so
it's input referred value does not change with PGA gain
code, see

Figure 6. The magnitude of the global offset

is controlled by bits V[1:0] in the mode register. (See
Table 1.)

V[1]

V[0]

Offset

0mV

25mV (default)

50mV

75mV

Table 1. Manual Global

Offset Programming

C D S

P G A

A D C

Automatic

Offset

Calibration

Manual

Global Offset

V[1:0]

C C D

Input

DB[9:0]

XRD9855/L55

Rev. 1.00

Preliminary

LOAD

SCLK

SDI

(LSB)

(MSB)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

AD0

AD1

TSC=50ns min.

Data Shifts on
Rising Edges

Load Internal Register

ADDRESS

Bit 1

Bit 0

DATA

TSET=10ns min.

Figure 7. Serial Port Timing Diagram

Table 2. Serial Interface Register Address Map

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Gain [7:0]

0 0 0 0 0 0 0 0 - minimum gain (6dB) *

1 1 1 1 1 1 1 1 - maximum gain (38 dB)

Table 3. Gain Register Bit Assignment

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Offset [7:0]

0 0 0 0 0 0 0 0 - do not use

0 0 0 0 0 0 0 1 - do not use

0 0 0 0 0 0 1 0 - minimum offset code

0 0 0 0 1 0 0 0 - typical offset code *

0 0 1 1 1 1 1 1 - maximum offset code

Table 4. Offset Register Bit Assignment

Note:

* Indicates default value

Address

Data

Name

AD1

AD0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Gain

Gain[7]

Gain[6]

Gain[5]

Gain[4]

Gain[3]

Gain[2]

Gain[1]

Gain[0]

Offset

Offset[7]

Offset[6]

Offset[5]

Offset[4]

Offset[3]

Offset[2]

Offset[1]

Offset[0]

Mode

V[1]

V[0]

Test3

Test2

Reset

Delay

Dp[2]

Dp[1]

Dp[0]

Dd[2]

Dd[1]

Dd[0]

Dr[1]

Dr[0]

XRD9855/L55

Rev. 1.00

Preliminary

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

V[1:0]

Test3

Test2

Reset

0 0 - 0mV offset

0 - Clamp only*

0 - RSTCCD*

0 - TestVin off*

0 - test off*

0 - auto detect*

0 - normal*

0 1 - 25mV offset*

1 - Clamp & Cal

1 - no RSTCCD

1 - TestVin on

1 - factory test

1 - manual

1 - reset

1 0 - 50mV offset

1 1 - 75mV offset

Table 5. Mode Register Bit Assignment

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Dp[2:0]

D [2:0]

Dr[1:0]

0 0 0 - SHP min delay *

0 0 0 - SHD min delay *

0 0 - RSTCCD min delay *

1 1 1 - SHP max delay

1 1 1 - SHD max delay

1 1 - RSTCCD max delay

Table 6. Delay Register Bit Assignment

Note:

* Indicates default value

SHP, SHD and RSTCCD Signals, M2 = 0

The SHP input to the XRD9855/XRD98L55 determines
when the Black level of each pixel is sampled. For
CLK_POL=high timing mode, the black level is
sampled on the falling edge of SHP. For
CLK_POL=low timing mode, the black level is sampled
on the rising edge of SHP.

The sampling edge of SHP should be positioned so that
it samples the pixel black level at a stable and repeat-
able point. The black level should be sampled after the
CCD output has had time to settle from the reset pulse
and before the output transitions to the video level (see
Figure 8). Aperture delay T

needs to be taken into

consideration when positioning the sampling edge of

SHP (see

Figure 8). This aperture delay is the time

from the sampling edge of SHP to the time the pixel
black level is actually sampled by the CDS. The
correct positioning of SHP will be 6-7 ns prior to where
the black level has adequately settled. This is typically
just before the CCD signal starts the transition to the
video level.

The SHD input to the XRD9855/XRD98L55 determines
when the Video level of each pixel is sampled. For
CLK_POL=high timing mode, the video level is
sampled on the falling edge of SHD. For
CLK_POL=low timing mode, the video level is sampled
on the rising edge of SHD.

XRD9855/L55

Rev. 1.00

Preliminary

SHP

SHD

CCD

Signal

RSTCCD

Pixel Black Level

Sample Point

Pixel Video Level

Sample Point

TBK

T VD

T RST

RSTCCD

Switch

Turn Off

Turn On

Reset Pulse

RSTCCD

Switch

Figure 8. CDS Timing Diagram

(CLK_POL = 1, M2 = 0)

The sampling edge of SHD should be positioned so that
it samples the pixel video level at a stable and repeat-
able point. The video level should be sampled after the
CCD output has settled from the black level and before
the output transitions to the reset pulse. Aperture
delay T

needs to be taken into consideration when

positioning the sampling edge of SHD (see

Figure 8).

This aperture delay is the time from the sampling edge
of SHD to the time the pixel video level is actually
sampled by the CDS. The correct positioning of SHD
will be 5-6 ns prior to where the video level has
adequately settled.

RSTCCD is intended to overlap the reset pulse of each
pixel. This is intended to eliminate the reset pulse
transients from getting into the XRD9855's CDS cir-
cuitry. Positioning of the RSTCCD signal so that it
overlaps the CCD signal reset pulse is not always
practical due to the timing generators being used or the
frequency at which the CCD is running. The most
critical thing to remember for RSTCCD is that it can not
be high when sampling either the black level or video
level.

XRD9855/L55

Rev. 1.00

Preliminary

CDS Clock Polarity

The CLK_POL pin is used to determine the polarity of
the CDS clocks (SHD, SHP, CLAMP). See

Figures 10

& 11, and Tables 7 & 8.

Event

Action

RSTCCD

Disconnect CDS Inputs from Reset

Noise

RSTCCD

Connect CDS Inputs and Track Black

Level

SHP

Hold Black Level and Track Video Level

SHD

Hold Video Level

SHP/SHD

No Action

Clamp High Activate DC Restore Clamp

Enable_Cal Activate Offset Calibration

High

Table 7. Timing Event Description

Table Valid for CLK_POL=1, M2=0

Event

Action

RSTCCD

Disconnect CDS Inputs from Reset

Noise

RSTCCD

Connect CDS Inputs and Track Black

Level

SHP

Hold Black Level and Track Video Level

SHD

Hold Video Level

SHP/SHD

No Action

Clamp Low

Activate DC Restore Clamp

Enable_Cal Activate Offset Calibration

High

Table 8. Timing Event Description

Table Valid for CLK_POL=0, M2=0

Line N

Line N+1

* Note: OB = Optically Black or Shielded pixels.

Active Video

Pixels

OB* pixels

Vertical Shift

Dummy &

OB* Pixels

EnableCal

Clamp

CCD Signal

RSTCCD

SHP

SHD

Active Video

Pixels

Figure 10. CCD Line Timing with CLK_POL = 1, M2 = 0

XRD9855/L55

Rev. 1.00

Preliminary

No RSTCCD Pulse Timing, M2 = 1

To help simplify the timing required to drive the
XRD9855 we have included a timing mode which does
not require an active signal for RSTCCD. To use this
timing, bit M2 in the timing mode register must be set
high.

In this timing mode, RSTCCD must be kept low. No
changes are required for the timing of the SHP and SHD
signals. The polarity of SHP, SHD and Clamp are still
controlled by the CLK_POL pin. The digital outputs
change on the sampling edge of SHD (see

Figure 12).

This mode can be used with both the XRD4460 timing
and the XRD9853 timing as described in the Line
Timing section.

Figure 12. XRD9855 Timing for no RSTCCD Pulse,

M2=1 & CLK_POL=1, RSTCCD=0

CCD Signal

RSTCCD

DB[9:0]

SHP

SHD

1
0

Pixel N

Data N-4

Data N-3

Data N-2

Data N-1

Data N

Line N

Line N+1

* Note: OB = Optically Black or Shielded pixels.

Active Video

Pixels

OB* Pixels

Vertical Shift

Dummy &

OB* Pixels

EnableCal

Clamp

CCD Signal

RSTCCD

SHP
SHD

Active Video

Pixels

CLK_POL=Low

Figure 11. CCD Line Timing with CLK_POL = 0, M2 = 0

XRD9855/L55

Rev. 1.00

Preliminary

Programmable Aperture Delays
Dp[2:0], Dd[2:0], Dr[1:0]

To help fine tune the pixel timing, the XRD9855 allows
the system to adjust the aperture delays associated
with SHP (T

), SHD (T

) and RSTCCD (T

RST

) by

programming the Aperture Delay serial port register.
On power up these three aperture delays are set to their
minimum values.

The SHP aperture delay is set by bits Dp[2:0]. Each
LSB adds approximately 2ns of delay. The SHD
aperture delay is set by bits Dd[2:0]. Each LSB adds
approximately 2ns of delay. The RSTCCD aperture
delay is set by bits Dr[1:0]. Each LSB adds approxi-
mately 4ns of delay.

Dp[2]

Dp[1]

Dp[0]

SHP Aperture

Delay T

(typ)

6ns (default)

8ns

10ns

12ns

14ns

16ns

18ns

20ns

Table 9. Programmable SHP Delays

Dd[2]

Dd[1]

Dd[0]

SHD Aperture

Delay T

(typ)

5ns (default)

7ns

9ns

11ns

13ns

15ns

17ns

19ns

Table 10. Programmable SHD Delays

Dr[1]

Dr[0]

RSTCCD Aperture

Delay T

RST

(typ)

3ns (default)

7ns

11ns

15ns

Table 11. Programmable RSTCCD Delays

Line Timing

At the beginning and/or end of every CCD line there are
a number of Optical black pixels. The XRD9855 uses
the output from these pixels for the DC Restore Clamp
and Black Level Offset Calibration functions. These
functions are controlled by the Clamp and/or EnableCal
pins.

The XRD9855 is designed to be compatible with the
Clamp Only timing of the XRD4460 or the Clamp &
EnableCal timing of the XRD9853. On power up the
chip will automatically detect which timing is being
used and make the necessary internal adjustments. If
EnableCal is high when Clamp is active, then "Clamp
Only" timing is selected (M3=0). If EnableCal is low
when Clamp is active, then "Clamp & Cal" timing is
selected (M3=1). If required, the automatic detection
function can be disabled through the serial port, and the
chip can be forced into one of the two timing modes by
programming mode register bits M3 & M1.

Clamp Only Timing (XRD4460 compatible)
M1=1, M3=0

In this mode EnableCal is held high, and Clamp is
activated during the Optical Black pixels.
The Clamp signal is used to trigger a one-shot which
controls the internal DC restore switch and the calibra-
tion logic. The DC restore switch is turned on for two
pixels after Clamp is activated. Then the Calibration
logic is enabled and runs until Clamp is deactivated.
The chip can be forced into this timing mode by
programming the Mode control register bits M1=1 and
M3=0.

XRD9855/L55

Rev. 1.00

Preliminary

Figure 13. Clamp Only Line Timing

CLK_POL=1, EnableCal=1, M1=1, M3=0, M2=0

CCD

Input

DB[9:0]

ADC

Bias

Clamp

Clamp Only Mode

DC Restore

Switch

EnableCal

PGA

CDS

Clk_Pol

Control

Logic

Offset

Calibration

Figure 14. Clamp Only Mode (XRD4460 Compatible)

M1=1, M3=0

Line N

Line N+1

* Note: OB = Optically Black or Shielded pixels.

Signal
Pixels

OB* Pixels

Signal

Pixels

Vertical Shift

Dummy &

OB* Pixels

(Horizontal Clocking Off)

EnableCal

Clamp

CCD Signal

RSTCCD

SHP

SHD

0
1

Internal Calibrate

Internal DC

Restore Switch

0
1

Minimum 10 OB Pixels

2 OB Pixels

XRD9855/L55

Rev. 1.00

Preliminary

Optical
Black
Pixels

(Shielded)

Active Video

Pixels

Dummy

Optical

Black

Pixels

Clamp & EnableCal Timing (XRD9853 Compatible)
M1=1, M3=1

In this mode EnableCal must be active during the large
number of Optical Black pixels (usually at the end of
each CCD line), Clamp should be active during the
Dummy pixels (usually at the beginning of each CCD
line).

The EnableCal pin (always active high) directly con-
trols the calibration logic.

The Clamp pin (polarity determined by CLK_POL)
controls only the DC restore switch at the CDS input.
EnableCal and Clamp must not be active at the same
time.

The chip can be forced into this timing mode by
programming the Mode control register bits M1=1 and
M3=1.

Figure 16. Clamp & EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0

Figure 15. Typical CCD Array with Active Pixels

& Optically Black Pixels

Line N

Line N+1

* Note: OB = Optically Black or Shielded Pixels.

Signal
Pixels

OB* Pixels

Signal

Pixels

Vertical Shift

Dummy &

OB Pixels

(Horizontal Clocking Off)

EnableCal

Clamp

CCD Signal

RSTCCD

SHP

SHD

Min. 2 Pixels

Min. 8 OB Pixels

XRD9855/L55

Rev. 1.00

Preliminary

Offset

Calibration

CCD

Input

DB[9:0]

ADC

bias

Clamp

Clamp & EnableCal Mode

EnableCal

PGA

CDS

Clk_Pol

DC Restore

switch

CDS/

Clock

Digital

STBY2

STBY1

PGA

ADC

Inputs

Outputs

Off

High-z

Off

High-z

Off

Figure 17. Clamp & Enable Cal Mode (XRD9853 Compatible),

M1=1, M3=3

Stand-by Mode (Power Down)

The STBY1 and STBY2 pins are used to put the chip
into the Stand-by or Power down mode. In this mode
all sampling and conversion stops, The digital outputs
are put into the high impedance mode, and the power
supply current will drop to less than 50

For most applications STBY1 and STBY2 should be
connected together and treated as a single control pin.
If an application uses the TestVin pin to access the
PGA output or the ADC input then STBY1 and STBY2
must be separately controlled, see the truth table
below.

Table 12. Stand-by Truth Table

XRD9855/L55

Rev. 1.00

Preliminary

Chip Reset

The chip has an Internal Power-On-Reset function to
ensure all internal control registers start up in a known
state. Pulling the Reset pin high or writing a logic 1 to
the Mode Registers reset bit will also reset the chip to
the Power-up default conditions.

Register

Default

Notes

Gain[7:0]

00000000

minimum gain

OS[7:0]

00001000

code 08 hex

V[1:0]

25 mV offset

Clamp only

RSTCCD required

Automatic timing detect On

Test3

Test modes off

Test2

Test modes off

Reset

reset bit will reset itself

Dp[2:0]

000

minimum delay

Dd[2:0]

000

minimum delay

Dr[1:0]

minimum delay

Table 13. Reset Conditions

Using TestVin (Pin 20)

The TestVin pin allows access to the input of the ADC,
or it can be used to monitor the CDS/PGA output. The
TestVin pin accesses the ADC input node through
switch S1 (see

Figure 18). This switch is controlled by

Bit3 of the serial port Test register. When the TEST3
bit of the mode register is high, switch S1 is "ON" and
the TestVin pin can be used to access the ADC input/
PGA output. When the TEST3 bit of the mode register
is low, switch S1 is "OFF" and the TestVin pin is
disconnected from the ADC input/PGA output.

To use TestVin as an auxiliary ADC input force
STBY2=low and STBY1=high. This will disable the
CDS/PGA and leave the ADC operating. If M2=0, the
ADC clock is generated from RSTCCD and SHP (

See

Figure 19). If M2=1, the ADC clock is generated from
SHP & SHD (

See Figure 20).

XRD9855/L55

Rev. 1.00

Preliminary

Mode Reg.

AD1

AD0

V[1]

V[0]

Test3

Test2

Reset

TestVin

Normal

Table 14. Serial Port Data to Use TestVin

Figure 18. Using TestVin to Access PGA Output & ADC Input

CDS

PGA

ADC

TestVin

CCD

Signal

RSTCCD

SHP

SHD

ADC Clock

(internal)

Track

Hold

ADC Data

CCD

Signal

RSTCCD

SHP

SHD

ADC Clock

(Internal)

Track

Hold

ADC Data

Figure 19. ADC Clock Generation,

CLK_POL=1, M2=0

Figure 20. ADC Clock Generation,

CLK_POL=1, M2=1

XRD9855/L55

Rev. 1.00

Preliminary

Digital Output Power Supplies

The DV

and DGND pins supply power to the digital

output drivers for pins DB[9:0], UNDER, and OVER.
DV

is isolated from V

so it can be at a voltage

level less than or equal to V

. This allows the digital

outputs to interface with advanced digital ASICs requir-
ing reduced supply voltages. For example V

can be

5.0 or 3.3V, while DV

is 2.5V.

Systems which use the same voltage level for both
analog and digital power supplies can take advantage
of the isolated DV

& DGND pins to reduce system

noise. The output drivers create large supply tran-
sients as they switch. Therefore DV

and DGND

should be routed separately from the analog V

GND to avoid injecting this noise into the analog power
network (see

Figure 21.)

Output

DGND

GND

Digital Output

Source-Body
Junction Diode

Between DV

& V

Source-Body
Junction Diode
Between
DGND & GND

Figure 21. DV

& DGND Digital Output Power Supplies,

> DV

There are no power supply sequencing issues if DV

and V

of the XRD9855/98L55 are driven from the

same supply. When DV

and V

are driven

separately, V

must come up at the same time or

before DV

, and go down at the same time or after

. If the power supply sequencing in this case is

not followed, then damage may occur to the product due
to current flow through the source-body junction diodes
between DV

and V

. An external diode (5082-

2235) layed out close to the converter from DV

prevents damage from occurring when power is

cycled incorrectly.

Note: V

must be greater than or equal to DV

or the

source-body diodes will be forward based.

Power Supply Sequencing

XRD9855/L55

Rev. 1.00

Preliminary

All of the GND pins, other than DGND, are tied to the
substrate and should be connected directly to the
analog ground plane under the XRD9855/XRD98L55.
The V

's should be supplied from a low noise, well

filtered regulator which derives the power supply volt-
age from the CCD power supply. All of the V

pins are

analog power supplies and should be locally decoupled
to the nearest GND pin with a 0.1

F, high frequency

capacitor. DV

and DGND are the power supplies for

the digital outputs and should be locally decoupled.
DV

and DGND should be connected to the same

power supply network as the digital ASIC which re-
ceives data from the XRD9855/XRD98L55.

In general, all traces leading to the XRD9855/
XRD98L55 should be as short as possible to minimize
signal crosstalk and high frequency digital signals from
feeding into sensitive analog inputs. The two CCD
inputs, In_Pos and In_Neg, should be routed as fully
differential signals and should be shielded and
matched. Efforts should be made to minimize the board
leakage currents on In_Pos and In_Neg since these
nodes are AC coupled from the CCD to the XRD9855/
XRD98L55. The digital output traces should be as short
as possible to minimize the capacitive loading on the
output drivers (see

Figure 22.)

General Power Supply and Board Design Issues

CCD

12V

5V/3V

Regulator

In_Neg

In_Pos

GND

DB[9:0]

DGND

XRD9855/XRD98L55

Digital

ASIC

DGND

5V/3V

Regulator

AGND

DGND

Figure 22. XRD9855/XRD98L55 Power Supply Connections

Application Note

If increasing the PGA Gain to code 128 (80h) or higher
causes a larger than expected offset increase in the
ADC digital output codes, the problem may be due to
the limited Automatic Offest Calibration range. This
problem may be solved by increasing the Global Offset
code, V[1:0], in the Mode Register. The default is
V[1:0] = 01 (binary). Try increasing to V[1:0] = 10, or
V[1:0] = 11.

XRD9855/L55

Rev. 1.00

Preliminary

Figure 23. XRD9855/XRD98L55 Application Schematic

CLK_POL=0

DB2

DB3

DB4

DGND

DB5

DB6

DB7

DB8

DB9

OVER

EnableCal

GND

Test

STBY1

STBY2

RESET

SCLK

LOAD

SDI

RTO

In_Neg

In_Pos

GND

RBO

CLAMP

SHD

SHP

RSTCCD

GND

CLK_POL

SYNC

UNDER

DB0

DB1

XRD9855/XRD98L55

Digital Data Bus

Serial

Interface

to CCD

Signal

to CCD

Ground

From Clock

Signal

Generator

0.01

0.1

from Clock Signal

Generator

0.1

XRD9855/L55

Rev. 1.00

Preliminary

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a user's specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.

Copyright 1998 EXAR Corporation
Datasheet December 1998
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Part Number XRD98L55