AT2004

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

Page 1 of 25

Š2001 Atelic System, Inc

Atelic Systems, Inc.

AT2004 Application Note

Preliminary

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

Version 1.0 January 29, 2001

Description

The AT2004 is a four full-duplex channels, ADPCM processor with conferencing and echo cancellation capabilities. It
follows the G.726 ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable

-law and A-

law input/output. It conforms to ITU G.165/G.168 Digital Adaptive Echo Canceller specification for line echo delay up to

20ms. Using the command serial interface, each individual half-channel can be independently configured for ADPCM,

conferencing and echo canceling features.

Features

4 full channels of ITU G.726 ADPCM

4 full channels of ITU G.165/G.168 compliant echo cancellation with up to 20ms echo delay

Fast and robust convergence for adaptive echo canceller, even in the presence of background noise

Nonlinear processing with adaptive suppression threshold and comfort noise generation for echo canceller

Per channel selectable

-Law and A-law input/output

On-chip time slot assignment

Available internal clock generator and frame sync. generator

Simple 3-wire serial command port for chip configuration

Conferencing capabilities for up to 3 additional sound sources

Applications

DECT

VoIP / VoDSL

Wireless telephone systems

Wireless PBX systems

Default Settings

4 channels of

-law PCM input on Xin in time slot 0, 1, 2, 3

4 channels of the corresponding ADPCM output at 32kbps on Xout in time slot 0, 1, 2, 3

4 channels of ADPCM input at 32kbps on Yin in time slot 0, 1, 2, 3

4 channels of corresponding PCM

-law output on Yout in time slot 0, 1, 2, 3

Echo cancellation enabled for four channels

Conferencing disabled

Note: To change the default settings, commands could be sent through the 3-wire interface.

AT2004

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

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Š2001 Atelic System, Inc

PIN Description

PIN

SYMBOL

TYPE

DESCRIPTION

XIN

X Channel Data In. Sampled on the falling edge of CLKP during

selected time slots with MSB first.

XOUT

X Channel Data Out. Updated on the rising edge of CLKP during

selected time slots with MSB first.

YIN

Y Channel Data In. Sampled on the falling edge of CLKA during

selected time slots with MSB first.

FSY

I/O

Y Channel Frame Sync. Master Y Channel Frame Sync. Signal
followed by the first time slot of transmission. It can be either
input or output by initial setup sequence.

YOUT

Y Channel Data Out. Updated on the rising edge of CLKA

during selected time slots with MSB first.

RSTZ

Reset. Low active signal to force chip reset.

13
12

XTAL1/MCLK
XTAL2

I
O

Crystal In & Out. 14.318 MHz Crystal connected

CLKP

I/O

PCM Clock. It can be either input created by external control

circuit, or output generated by internal control circuit.

CLKA

I/O

ADPCM Clock. It can be either input created by external control

circuit, or output generated by internal control circuit.

18
15
11
10

SYNC1
SYNC2
SYNC3
SYNC4

O
O
O
O

Sync 1. Frame sync. for 1

CODEC.

Sync 2. Frame sync. for 2

CODEC.

Sync 3. Frame sync. for 3

CODEC.

Sync 4. Frame sync. for 4

CODEC.

4
3

TM1
TM0

I
I

TM1 &TM0. Tie to Ground for normal operation.

7
6

A1
A0

I
I

A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire

serial port can be enabled for configuration.

SDI/SDO

I/O

Serial Data In. Data for configuration on the fly by 3-wire serial

port. Sampled on the rising edge of SCLK with LSB first.
Serial Data Out. Output data after sending Read Memory

command by 3-wire serial port. Sampled on the rising edge of
SCLK with LSB first.

SCLK

Serial Clock. Used to write to the 3-wire serial port registers or
output data from 3-wire serial port registers.

SCSZ

Serial Port Chip Select. Low active to enable 3-wire serial port.

Power. 3.3 Volts.

14
19

Vss1
Vss2

-
-

Ground. 0 Volt.

For clock source other than 14.318MHz, please contact Atelic Systems.

AT2004

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

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Š2001 Atelic System, Inc

AT2004 PIN Assignment

28-PIN SOP

NC 1

RSTZ 2

TM0 3

TM1 4

NC 5

A0 6

A1 7

NC 8

NC 9

SYNC4 10

SYNC3 11

XTAL2 12

XTAL1 13

VSS1 14

VDD

YIN

CKLA

FSY

YOUT

SCSZ

SDI/SDO

SCLK

XOUT

VSS2

SYNC1

CLKP

XIN

SYNC2

AT2004 SOP Pin Assignment

When there are multiple AT2004 used on the same system, A1, A0 are used to identify the chip.

A1, A0 are for chip ID. Values are from 00 to 03. They should be connected to microcontroller I/O line or hard wired to either VCC or ground.

AT2004

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

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Š2001 Atelic System, Inc

AT2004 Function Block Diagram

8-bit
PCM

ADPCM
Signal

LawA

8-bit PCM

Conferencing up to 3 sources

Law to

Linear

ADPCM
Encoder

ADPCM
Decoder

Linear

to Law

Gain

Linear

to Law

U
X

ADPCM

Reset

Law to

Linear

U
X

ADPCM
Bypass

LawP

LawA

ADPCM
Bypass

U
X

Channel
Bypass

ADPCM

Reset

U
X

ADPCM

Reset

U
X

Channel
Bypass

Reset

Echo

Canceller**

EC
Reset

U
X

**Please refer to the next page

AT2004

4 Channels ADPCM Processor with Echo Cancellation and Conferencing

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Š2001 Atelic System, Inc

Echo Canceller Block Diagram:

Remover

NLP

U
X

Adaptive

Filter

Remover

Double Talk

Detector

Narrow Band

Signal Detector

Disabling Tone

Detector

No. 5, 6, 7

Signalling Tone

Detector

Dc_rmv

Comfort

Noise NLP_flag

Bypass

Stepsize

Freeze

Dc_rmv

Tone_flag

A dotted line with arrow mark indicate the control bit in the per channel control command, such
as LawP, EC reset, LawA, ADPCM bypass, ADPCM reset, Channel bypass, Dc_rmv, Comfort

noise, NLP_flag, EC bypass, Stepsize, Freeze and Tone_flag. Please refer to page 10, 11 and

12 for detail information.

Only one full channel is shown. AT2004 has additional capability to process up to 4 full
channels simultaneously.

Note:

Part Number AT2004