32K x 8
Radiation Hardened
Static RAM 5 V

167A690
182A934

BAE SYSTEMS ˇ 9300 Wellington Road ˇ Manassas, Virginia 20110-4122

Product Description

Radiation

ˇ Fabricated with Bulk CMOS 0.8 ľm Process

ˇ Total Dose Hardness through 1x10

rad(Si)

ˇ Neutron Hardness through 1x10

N/cm

ˇ Dynamic and Static Transient Upset Hardness

through 1x10

rad(Si)/s

ˇ Soft Error Rate of < 1x10

-11

Upsets/Bit-Day

ˇ Dose Rate Survivability through 1x10

rad(Si)/s

ˇ Latchup Free

Features

Other

ˇ Read/Write Cycle Times

30 ns (-55 °C to 125°C)

ˇ SMD Number 5962H92153

ˇ Asynchronous Operation

ˇ CMOS or TTL Compatible I/O

ˇ Single 5 V ą10% Power Supply

ˇ Low Operating Power

ˇ Packaging Options

ˇ 36-Lead Flat Pack (0.630" x 0.650")
ˇ 28-Lead DIP, MIL-STD-1835, CDIP2-T28

General Description

The 32K x 8 radiation hardened static RAM is a
high performance, low power device designed
and fabricated in 0.8 ľm Radiation Hardened
Complementary Metal Oxide Semiconductor
(RHCMOS) technology. BAE SYSTEMS' device
is designed for radiation environments using
industry standard functionality. The memory can
be personalized for either CMOS or Transistor
Transistor Logic (TTL) input receivers. The
SRAM operates over the full military temperature
range and requires a single 5 V ą10% power
supply. Power consumption is typically less than
20 mW/MHz in operation, and less than 10 mW in
the low power disabled mode. The SRAM read
operation is fully asynchronous, with an
associated typical access time of 20
nanoseconds.

BAE SYSTEMS' bulk CMOS technology achieves
radiation hardening via a combination of process
technology enhancements and specific circuit
improvements.

Functional Diagram

Signal Definitions

A: 0-14

DQ: 0-7

Address input pins that select a particular

eight-bit word within the memory array.

Bi-directional data pins that serve as data

outputs during a read operation and as data
inputs during a write operation.

Negative chip select, when at a low level,

allows normal read or write operation. When
at a high level, S forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and
disables the data input buffers only. If this
signal is not used, it must be connected to
GND.

Negative write enable, when at a low level, activates a

write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.

Negative output enable, when at a high level holds the

data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S,
W, and E. If this signal is not used it must be connected
to GND.

Chip enable, when at a high level allows normal

operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S input buffer. If this signal is not used, it
must be connected to V

Notes:

1) V

for don't care (X) inputs = V

or V

2) When G = high, I/O is high-Z.

3) To dissipate the minimum amount of

standby power when in standby mode:
S= V

and E = GND. All other input

levels may float.

4) E is tied high internally to the chip for

the 28-DIP package.

Truth Table

Mode

Inputs

(1),(2)

(4)

High

Low

High

Low

High

G
X

Low

I/O

Data-In

Data-Out

High-Z

Power

Active

Standby

Write

Read

Standby

(3)

ˇ ˇ ˇ

A:11

Column Decoder

Data Input/Output

32,768 x 8

Memory Array

Row Decoder

DQ:8

A:4

Notes:

Note:

1)All voltages referenced to GND.

The substrate of this module is connected directly to Ground.

Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:

ˇ Power-Up Sequence: GND, V

, Inputs

ˇ Power-Down Sequence: Inputs, V

, GND

Absolute Maximum Ratings

Recommended Operating Conditions

Power Sequencing

Minimum

+4.5

0.0

-55

0.0

+2.0

+3.5

Units

Volt

Celsius

Volt

Supply Voltage

Parameters

(1)

Supply Voltage Reference

Case Temperature

Input Logic "Low" - CMOS

Input Logic "Low" - TTL

Input Logic "High" - TTL

Input Logic "High" - CMOS

Symbol

GND

Maximum

+5.5

0.0

+125

+1.5

+0.8

Minimum

-65°C

-55°C

-0.5 V

(Class II)

Storage Temperature Range (Ambient)

Applied Conditions

(1)

Operating Temperature Range (T

CASE

)

Positive Supply Voltage

Input Voltage

(2)

Output Voltage

(2)

Power Dissipation

(3)

Lead Temperature (Soldering 5 sec)

Electrostatic Discharge Sensitivity

(4)

Maximum

+150°C

+125°C

+7.0 V

+ 0.5 V

2.0 W

+250°C

+ 0.5 V

1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.

2) Maximum applied voltage shall not exceed +7.0 V.

3) Guaranteed by design; not tested.

4) Class as defined in MIL-STD-883, Method 3015.

1) Typical operating conditions: V

= 5.0V; TA = 25 °C, pre-radiation.

-55°C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

2) The worst case timing sequence of t

WLZQ

+ t

DUWH

+ t

WHWL

= t

AVAV

300 ą 10%

2.8V

50 pF + 10%

Output Load Circuit

DC Electrical Characteristics

Note:

Symbol

Test Conditions

(1)

Device Type

Limits

Minimum

Maximum

Units

DD1

F = F

MAX

= 1/t

AVAV(min)

S = V

= GND

E = V

= V

No Output Load

S = V

= V

E = V

= GND

F = F

MAX

= 1/t

AVAV(min)

= 2.5 V

= V

0 V

5.5 V

By Design/
Verified By
Characterization

= -200 ľA

= -4 mA

= 200 ľA

= 8 mA

X3X
X4X
X6X

All

2.0
1.2
2.0

4.2

2.5

3.5

2.0

-5

-10

0.4

- 0.5 V

0.05

1.5

0.8

X3X

180

mA
mA
mA

ľA

Test

Supply Current
(Cycling Selected)

Supply Current
(Cycling De-Selected)

Supply Current
(Standby)

Data Retention Current

Data Retention Voltage

High Level Input Voltage

Low Level Input Voltage

Input Leakage

Output Leakage

out

High Level Output Voltage

Low Level Output Voltage

CMOS

TTL

DD2

DD3

ILK

OLK

F = F

MAX

= 1/t

AVAV(min)

S = V

= V

E = V

= GND

0 V

OUT

5.5 V

By Design/
Verified By
Characterization

CMOS

TTL

X4X
X6X

130

X3X
X4X
X6X

2.0
1.2
2.0

mA
mA
mA

X3X
X4X
X6X

1.0
0.4
1.0

mA
mA
mA

(2)

Note:

1)Test conditions: input switching levels V

= 0.5 V/V

-0.5 V (CMOS), V

= 0 V/3 V (TTL), input rise

and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics
table, capacitive output loading C

= 50 pF. For C

> 50 pF, derate access times by 0.02 ns/pF (typical).

-55 °C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

Read Cycle AC Timing Characteristics

(1)

Read Cycle Timing Diagram

Valid Address

Valid Data

High Impedance

Address

Data
Out

AVAV

AVQV

SLQV

SLQX

EHQV

EHQX

GLQV

GLQX

AXQX

SHQZ

ELQZ

SHQZ

Worst Case By Speed

Units

Test

Read Cycle Time

Output Hold After Address Change

Chip Select to Output Active

Chip Enable to Output Active

Output Enable to Output Active

Address Access Time

Chip Select Access Time

Chip Enable Access Time

Chip Select to Output Disable

Chip Disable to Output Disable

Output Enable to Output Disable

Output Enable Access Time

Minimum or

Maximum

Minimum

Maximum

Symbol

AVAV

AVQV

AXQX

SLQV

SLQX

SHQZ

EHQV

EHQX

ELQZ

GLQV

GLQX

GHQZ

-60

-40

CMOS - 15

TTL - 18

-30

CMOS - 10

TTL - 12

CMOS - 10

TTL - 12

CMOS - 12

TTL - 15

CMOS - 10

TTL - 12

Note:

1) Test conditions: input switching levels V

= 0.5 V/V

- 0.5 V (CMOS), V

= 0 V/3 V (TTL), input rise and

fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table,
capacitive output loading = 50 pF. -55°C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

AVAV

Valid Address

Valid Data

High Impedance

Address

AVWH

SLWH

EHWH

WLWH

AVWL

WLQZ

WHQX

WHDX

WHWL

DVWH

Data
Out

Data
In

WHAX

Write Cycle AC Timing Characteristics

(1)

Write Cycle Timing Diagram

Worst Case By Speed

Minimum or

Maximum

Minimum

Maximum

Minimum

-40

Units

Test

Write Cycle Time

Chip Select to End of Write

Address Setup to End of Write

Write Pulse Width Access Time

Write Pulse Width

Data Setup to End of Write

Address Setup to Start of Write

Data Hold After End of Write

Write Enable to Output Disable

Chip Enable to End of Write

Output Active After End of Write

Address Hold After End of Write

Minimum

-60

-30

Symbol

AVAV

WLWH

SLWH

DVWH

AVWH

WHDX

AVWL

WHAX

WLQZ

WHQX

WHWL

EHWH

ELWH

Dynamic Electrical Characteristics

Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (S), or chip
enable (E) (refer to Read Cycle Timing diagram). To
perform a valid read operation, both chip select and output
enable (G) must be low and chip enable and write enable
(W) must be high. The output drivers can be controlled
independently by the G signal. Consecutive read cycles can
be executed with S held continuously low, and with E held
continuously high, and toggling the addresses.

For an address-activated read cycle, S and E must be valid
prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid t

AVQV

time following the latest

occurring address edge transition. The minimum address
activated read cycle time is t

AVQV

. When the RAM is

operated at the minimum address-activated read cycle time,
the data outputs will remain valid on the RAM I/O until t

AXQX

time following the next sequential address transition.

To control a read cycle with S, all addresses and E must be
valid prior to or coincident with the enabling S edge
transition. Address or E edge transitions can occur later
than the specified setup times to S; however, the valid data
access time will be delayed. Any address edge transition,
that occurs during the time when S is low, will initiate a new
read access, and data outputs will not become valid until
t

AVQV

time following the address edge transition. Data

outputs will enter a high impedance state t

SHQZ

time

following a disabling S edge transition.

To control a read cycle with E, all addresses and S must be
valid prior to or coincident with the enabling E edge
transition. Address or S edge transitions can occur later
than the specified setup times to E; however, the valid data
access time will be delayed. Any address edge transition
that occurs during the time when E is high will initiate a new
read access, and data outputs will not become valid until
t

AVQV

time following the address edge transition. Data

outputs will enter a high impedance state t

ELQZ

time

following a disabling E edge transition.

Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable (W),
chip select (S), or chip enable (E) edge transitions (refer
to Write Cycle Timing diagrams). To perform a write
operation, both W and S must be low, and E must be
high. Consecutive write cycles can be performed with W
or S held continuously low, or E held continuously high. At
least one of the control signals must transition to the
opposite state between consecutive write operations.

The write mode can be controlled via three different
control signals: W, S, and E. All three modes of control
are similar except the S and E controlled modes actually
disable the RAM during the write recovery pulse. Only the
W controlled mode is shown in the table and diagram on
the previous page for simplicity. However, each mode of
control provides the same write cycle timing
characteristics. Thus, some of the parameter names
referenced below are not shown in the write cycle table or
diagram, but indicate which control pin is in control as it
switches high or low.

To write data into the RAM, W and S must be held low
and E must be held high for at least t

WLWH

SLSH

EHEL

time.

Any amount of edge skew between the signals can be
tolerated and any one of the control signals can initiate or
terminate the write operation. For consecutive write
operations, write pulses must be separated by the
minimum specified t

WHWL

SHSL

ELEH

time. Address inputs

must be valid at least t

AVWL

AVSL

AVEH

time before the

enabling W/S/E edge transition, and must remain valid
during the entire write time. A valid data overlap of write
pulse width time of t

DVWH

DVSH

DVEL

, and an address valid to

end of write time of t

AVWH

AVSH

AVEL

also must be provided

for during the write operation. Hold times for address
inputs and data inputs with respect to the disabling W/S/E
edge transition must be a minimum of t

WHAX

SHAX

ELAX

time

and t

WHDX

SHDX

ELDX

time, respectively. The minimum write

cycle time is t

AVAV

Radiation Characteristics

Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after a total ionizing radiation dose of 1x10

rad(Si). All

electrical and timing performance parameters will remain
within specifications after rebound at V

= 5.5 V and T =

125°C extrapolated to ten years of operation. Total dose
hardness is assured by wafer level testing of process monitor
transistors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations
have been made between 10 keV X-rays applied at a dose
rate of 1x10

rad(Si)/min at T = 25°C and gamma rays (Cobalt

60 source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test environments.

Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining stored
data during and after exposure to a transient ionizing radiation
pulse of

50 ns duration up to 1x10

rad(Si)/s, when applied

under recommended operating conditions. To ensure validity
of all specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation is

10%), stiffening capacitance can be placed on

the package between the package (chip) V

and GND with

the inductance between the package (chip) and stiffening
capacitance kept to a minimum. If there are no operate-
through or valid stored data requirements, typical de-coupling
capacitors should be mounted on the circuit board as close as
possible to each device.

The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse of

50 ns

duration up to 1x10

rad(Si)/s, when applied under

recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must
accommodate these effects.

Neutron Radiation
The SRAM will meet any functional or timing specification
after a total neutron fluence of up to 1x10

-2

applied

under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.

Soft Error Rate
The SRAM has a soft error rate (SER) performance of
<1x10

-11

upsets/bit-day, under recommended operating

conditions. This hardness level is defined by the Adams
90% worst case cosmic ray environment.

Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions.

Radiation Hardness Ratings

(1),(2)

Notes:
1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan.
2) Device electrical characteristics are guaranteed for post irradiation levels at 25°C.
3) 90% worst case particle environment, geosynchronous orbit, 0.025'' of aluminum shielding.

Specification set using the CREME code upset rate calculation method with a 2 ľm epi thickness.

4) Immune for LET

120 MeV/mg/cm

Conditions

Characteristics

Total Dose

Single Event Upset

(3)

Prompt Dose Upset

Single Event Induced Latchup

Survivability

Single Event Upset

(3)

Neutron Fluence

Units

rad(Si)

Upsets/Bit-Day

rad(Si)/s

Immune

(4)

rad(Si)/s

Upsets/Bit-Day

N/cm

Maximum

1E - 10

1E - 11

Symbol

RTD

SEU2

RPRU

SEL

SEU1

RNF

Minimum

1E + 06

1E + 09

1E + 12

1E + 14

20 - 50 ns Pulse Width
T

case

= 25°C and 125°C

MIL-STD-883, TM 1019.5
Condition A

20 - 50 ns Pulse Width
T

case

= 125°C

-55°C

case

80°C

-55°C

case

125°C

-55°C

case

125°C

= 5.5 V

*Input rise and fall times <5 ns

Tester AC Timing Characteristics

Radiation Hardness Assurance

Reliability

BAE SYSTEMS' reliability starts with an overall product
assurance system that utilizes a quality system involving all
employees including operators, process engineers and
product assurance personnel. An extensive wafer lot
acceptance methodology, using in-line electrical data as well
as physical data, assures product quality prior to assembly. A
continuous reliability monitoring program evaluates every lot
at the wafer level, utilizing test structures as well as product
testing. Test structures are placed on every wafer, allowing
correlation and checks within-wafer, wafer-to-wafer, and from
lot-to-lot.

Reliability attributes of the CMOS process are characterized
by testing both irradiated and non-irradiated test structures.
The evaluations allow design model and process changes to
be incorporated for specific failure mechanisms, i.e., hot
carriers, electromigration, and time dependent dielectric
breakdown. These enhancements to the operation create a
more reliable product.

The process reliability is further enhanced by accelerated
dynamic life tests of both irradiated and non-irradiated test
structures. Screening and testing procedures from the
customer are followed to qualify the product.

A final periodic verification of the quality and reliability of the
product is validated by a TCI (Technology Conformance
Inspection).

BAE SYSTEMS has two QML screen levels (Q and V) to meet
full compliant space applications. For limited performance and
evaluation situations, BAE SYSTEMS offers an engineering
screen level.

Screening Levels

BAE SYSTEMS provides a superior quality level of radiation
hardness assurance for our products. The excellent product
quality is sustained via the use of our qualified QML operation
which requires process control with statistical process control,
radiation hardness assurance procedures and a rigid
computer controlled manufacturing operation monitoring and
tracking system.

The BAE SYSTEMS technology is built with resistance to
radiation effects. Our product is designed to exhibit < 1e

-11

fails/bit-day in a 90% worst case geosynchronous orbit under
worst case operating conditions. Total dose hardness is
assured by irradiating test structures on every lot and total
dose exposure with Cobalt 60 testing performed quarterly on
TCI lots to assure the product is meeting the QML radiation
hardness requirements.

TTL I/O Configuration

CMOS I/O Configuration

3 V

- 0.4 V

3.4 V

0.4 V

2.4 V

1.5 V

High Z

High Z = 2.9 V

0 V

1.5 V

. . . . . . . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . .

. . . . .

. . . . . . . .

. . . .

0.5 V

Input

Levels*

Output

Sense

Levels

3.4 V

0.4 V

2.4 V

High Z

High Z = 2.9 V

- 0.4 V

- 0.5 V

Pin Listing

Standard Screening Procedure

Stress Methodology

There are two methods of burn-in defined. For "Static" burn-in,
all possible addresses are written with a logic "1" for half of the
burn-in duration and a logic "0" for the remaining half. For
"Dynamic" burn-in, all possible addresses are written with
alternating high and low data.

All I/O pins specified in the static and dynamic burn-in pin lists
are driven through individual series resistors (1.6K

ą10%).

The burn-in circuit diagram is shown at right.

Voltage Levels
ˇ Vin(0): 0.0 V to + 0.4 V

= Low level for all programmed signals

ˇVin(1): + 5.4 V to + 6.0 V

= High level for all programmed signals

ˇ V1: + 5.5 V (-0% / +10%)

All V

pins are tied to this level

ˇVsx: Float or GND

All GND pins are tied to this level

C1 = 0.1 ľF (ą10%)
R = 1.6K

(ą10%)

DQ0

DIN

DQ7

A14

32K x 8

SRAM

The dynamic
burn-in pin listing
is shown at right.
F = square wave,
100 KHz to
1.0 MHz.

Sample

Alternate Method Used

Die Traceability

MIL-STD-883, TM 2010

5.5 V, 125°C, 144 Hours

Meets Group A

< 5% Fallout

MIL-STD-883, TM 2009

Wafer Lot Acceptance

Serialization

Destructive Bond Pull

Internal Visual

Temperature Cycle

Constant Acceleration

PIND

Radiography

Electrical Test

Dynamic Burn-In

Electrical Test

Static Burn-In

Final Electrical

PDA

Fine and Gross Leak

External Visual

Comments

Flow

QML Level

Burn-In Circuit

Input

Signal

F/2

F/4

F/8

F/16

F/32

Input

A11

A12

A13

A14

A10

Signal

F/131072

F/65536

Signal

F/8192

F/16384

F/32768

F/4096

F/2048

Input

A6
A7

Signal

F/128

F/256

F/512

F/1024

F/64

Packaging

36-Lead Flat Pack Pinout

28-Lead DIP Pinout

36-Lead Flat Pack

The 32K x 8 SRAM is offered in a custom 36-lead FP,
36-lead FPP or standard 28-lead DIP. All packages are
constructed of multilayer ceramic (AI

) and feature

internal power and ground planes. The FP also features
a non-conductive ceramic tie bar on the lead frame.
The purpose of the tie bar is to allow electrical testing of
the device, while preserving the lead integrity during
shipping and handling, up to the point of lead forming
and insertion.

Optional capacitors can be mounted to the package to
maximize supply noise decoupling and increase board
packing density. These capacitors attach directly to the
internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire
and package, both of which are critical in a transient
radiation environment. All NC pins must be connected to
either V

, GND or an active driver to prevent charge

build up in the radiation environment. (NC = no connect.)

A14

A12

DQ0

DQ1

DQ2

GND

Top

View

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Top

View

GND

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

GND

A14

A12

DQ0

DQ1

DQ2

GND

Lead 1 Indicator

Lead 36

Lead 1

Lead 19

Lead 18

(2)

(1)

(
U

)

D

t
e

(Width)

(Pitch)

GND

Notes:

1) Part mark per device specification.

2) "QML" may not be required per device

specification.

3) Dimensions are in inches.

4) Lead width: .008 ą .002.

5) Lead height: .006 ą .002.

6) Unless otherwise specified, all

tolerances are ą .005".

A=.085 ą .010
B=.008 ą .002
C=.013 ą .004
D=.650 ą .010
E=.025 ą .002
F=.630 ą .007
G=.425 ą .004
H=1.490

J=.135
K=.080
L=.020
M=.285
N=.100
P=.040
Q=.130
R=.260

Cleared for Public Domain Release

BAE SYSTEMS ˇ 9300 Wellington Road ˇ Manassas, Virginia 20110-4122

BAE SYSTEMS
An ISO 9001, AS9000, ISO 14001,
and SEI CMM Level 4 Company
9300 Wellington Road, Manassas, VA 20110-4122
866-530-8104
http://www.iews.na.baesystems.com/space/

0041_32K_8_SRAM.ppt

BAE SYSTEMS reserves the right to make
changes to any products herein to improve
reliability, function or design. BAE
SYSTEMS does not assume liability arising
out of the application or use of any product
or circuit described herein, neither does it
convey any license under its patent rights
nor the rights of others.

Ordering Information

For 28-Lead DIP description, see
MIL-STD-1835, type CDIP2-T28,
configuration C, dimensions D-10.

36-Lead Flat Pack with Pedestal Package

Notes:

1) Part mark per device specification.

2) "QML" may not be required per device

specification.

3) Dimensions are in inches.

4) Lead width: .008 ą .002.

5) Lead height: .006 ą .002.

6) Unless otherwise specified, all

tolerances are ą .005".

A=.137 ą .010
B=.008 ą .002
C=.013 ą .004
D=.650 ą .010
E=.025 ą .002
F=.630 ą .007
G=.425 ą .004

H=1.490
J=.135
K=.450
L=.285

28-Lead DIP

32K x 8 CMOS Memory Device
ˇPart Number 167A690

32K x 8 TTL Memory Device
ˇPart Number 182A934

Screen

Designation

1=QML VV
3=Engineering
4=QML VQ
5=QML QQ
7=Customer Specific

Speed

Designation

3 = 30 ns
4 = 40 ns

Package

Designation

1 = 36-Lead FP

2 = 36-Lead FPP

3 = 28-Lead DIP

Lead 1 Indicator

GND

(1)

Lead 1

Lead 18

Lead 36

Lead 19

QML (USA) Date Code

(2)

6 = 60 ns