EL4581C

January

1996

Rev

EL4581C

Sync Separator 50% Slice S-H Filter

Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation

1993 Elantec Inc

Features

NTSC PAL and SECAM sync

separation

Single supply

Precision 50% slicing internal

caps

Built-in color burst filter
Decodes non-standard verticals
Pin compatible with LM1881
Low power
Typically 1 5 mA supply current
Resistor programmable scan rate
Few external components
Available in 8-pin DIP and SO-8

pkg

Applications

Video special effects
Video test equipment
Video distribution
Displays
Imaging
Video data capture
Video triggers

Ordering Information

Part No

Temp Range

Package Outline

EL4581CN b40 C to a85 C 8-Pin DIP MDP0031

EL4581CS b40 C to a85 C 8-Lead SO MDP0027

Demo Board

A dedicated demo board is not
available However this device can
be placed on the EL4584 5 Demo
Board

General Description

The EL4581C extracts timing information from standard nega-
tive going video sync found in NTSC PAL and SECAM broad-
cast systems It can also be used in non standard formats and
with computer graphics systems at higher scan rates by adjust-
ing a single external resistor When the input does not have
correct serration pulses in the vertical interval a default verti-
cal output is produced

Outputs are composite sync vertical sync burst back porch
output and odd even output The later operates only in inter-
laced scan formats

The EL4581C provides a reliable method of determining correct
sync slide level by setting it to the mid-point between sync tip
and blanking level at the back porch This 50% level is deter-
mined by two internal self timing sample and hold circuits that
track sync tip and back porch levels This also provides a degree
of hum and noise rejection to the input signal and compensates
for varying input levels of 0 5 p-p to 2 0 Vp-p

A built in linear phase third order low pass filter attenuates
the chroma signal in color systems to prevent incorrectly set
color burst from disturbing the 50% sync slide

This device may be used to replace the industry standard
LM1881 offering improved performance and reduced power
consumption

The EL4581C video sync separator is manufactured using
Elantec's high performance analog CMOS process

Connection Diagram

EL4581C SO P-DIP Packages

4581 1

Top View

Manufactured under U S Patent No 5 528 303

EL4581C

Sync Separator 50% Slice S-H Filter

Absolute Maximum Ratings

25 C)

Supply

Storage Temperature

65 C to

150 C

Lead Temperature

260 C

Pin Voltages

0 5V to V

0 5V

Operating Temperature Range

40 C to

85 C

Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T

Test Level

Test Procedure

100% production tested and QA sample tested per QA test plan QCX0002

100% production tested at T

25 C and QA sample tested at T

25 C

MAX

and T

MIN

per QA test plan QCX0002

III

QA sample tested per QA test plan QCX0002

Parameter is guaranteed (but not tested) by Design and Characterization Data

Parameter is typical value at T

25 C for information purposes only

DC Electrical Characteristics

Unless otherwise state V

5V T

25 C R

set

680 k

Parameter

Description

Temp

Min

Typ

Max

Test

Units

Level

5V (Note 1)

25 C

0 75

1 7

Clamp Voltage

Pin 2 Unloaded

25 C

1 3

1 5

1 9

Discharge Current

Pin 2

25 C

Clamp Charge Current

Pin 2 V

25 C

Ref Voltage

Pin 6 V

5V (Note 2)

25 C

1 5

1 8

2 1

Output Low Voltage

1 6 mA

25 C

800

Output High Voltage

e b

25 C

e b

1 6 mA

2 4

Note 1 No video signal outputs unloaded
Note 2 Tested for V

5% which guarantees timing of output pulses over this range

18in

EL4581C

Sync Separator 50% Slice S-H Filter

Dynamic Characteristics

5V I

pk-pk video T

25 C C

15 pF I

e b

1 6 mA I

1 6 mA Signal voltages are peak to peak

Parameter

Description

Temp

Min

Typ

Max

Test

Units

Level

Vertical Sync Width t

(Note 3)

25 C

190

230

300

Burst Back Porch Width t

(Note 3)

25 C

2 5

3 5

4 5

Vertical Sync Default Delay t

VSD

25 C

Filter Attenuation

3 4 MHz (Note 4)

25 C

Composite Sync Prop Delay

Composite Sync

25 C

260

400

(Note 3)

Input Dynamic Range

p-p NTSC Signal

25 C

0 5

(Note 5)

Slice Level

Input Voltage

P-P

25 C

40%

50%

60%

(Note 6)

Full

40%

50%

60%

Note 3 C S Vertical and Burst outputs are all active low

2 4V V

0 8V

Note 4 Attenuation is a function of Rset (PIN6)
Note 5 Typical min is 0 3 V

P-P

Note 6 Refers to threshold level of sync tip to back porch amplitude

Pin Descriptions

Pin No

Pin Name

Function

Composite Sync Out

Composite sync pulse output Sync pulses start on a falling edge and end on a rising edge

Composite Video in

AC coupled composite video input Sync tip must be at the lowest potential (Positive

picture phase)

Vertical Sync Out

Vertical sync pulse output The falling edge of Vert Sync is the start of the vertical period

GND

Supply ground

Burst Back Porch Output

Burst Back porch output Low during burst portion of composite video

SET

An external resistor to ground sets all internal timing 681k 1% resistor will provide correct

timing for NTSC signals

Odd Even Output

Odd Even field output Low during odd fields high during even fields Transitions occur at

start of Vert Sync pulse

Positive supply (5V)

Note R

SET

must be a 1% resistor

20in

EL4581C

Sync Separator 50% Slice S-H Filter

Description of Operation

A simplified block schematic is shown in Figure
2 The following description is intended to pro-
vide the user with sufficient information to be
able to understand the effects that the external
components and signal conditions have on the
outputs of the integrated circuit

The video signal is AC coupled to pin 2 via the
capacitor C

nominally 0 1

mF The clamp circuit

A1 will prevent the input signal on pin 2 going
any more negative than 1 5V the value of refer-
ence voltage V

Thus the sync tip the most

negative part of the video waveform

will be

clamped at 1 5V The current source I

nominal-

ly 10

mA charges the coupling capacitor during

the remaining portion of the H line approxi-
mately 58

ms for a 15 75 kHz timebase From

V the video time-constant can be

calculated It is important to note that the charge
taken from the capacitor during video must be
replaced during the sync tip time which is much
shorter (ratio of x 12 5) The corresponding cur-
rent to restore the charge during sync will there-
fore be an order of magnitude higher and any
resistance in series with C

will cause sync tip

crushing For this reason the internal series re-
sistance has been minimized and external high
resistance values in series with the input cou-
pling capacitor should be avoided The user can
exercise some control over the value of the input
time constant by introducing an external pull-up
resistance from pin 2 to the 5V supply The maxi-
mum voltage across the resistance will be V

less 1 5V for black level For a net discharge cur-
rent greater than zero the resistance should be
greater than 450k This will have the effect of
increasing the time constant and reducing the de-
gree of picture tilt The current source I

directly

tracks reference current I

and thus increases

with scan rate adjustment as explained later

The signal is processed through an active 3 pole
filter (F1) designed for minimum ripple with con-
stant phase delay The filter attenuates the color
burst by 24 dB and eliminates fast transient
spikes without sync crushing An external filter
is not necessary The filter also amplifies the

video signal by 6 dB to improve the detection
accuracy Note that the filter cut-off frequency is
a function of RSET through I

and is propor-

tional to I

Internal reference voltages (block V

REF

) with

high immunity to supply voltage variation are
derived on the chip Reference V

with op-amp

A2 forces pin 6 to a reference voltage of 1 7V
nominal Consequently it can be seen that the
external resistance RSET will determine the val-
ue of the reference current I

The internal re-

sistance R3 is only about 6 k

X much less than

RSET All the internal timing functions on the
chip are referenced to I

and have excellent

supply voltage rejection

Comparator C2 on the input to the sample and
hold block (S H) compares the leading and trail-
ing edges of the sync pulse with a threshold volt-
age V

which is referenced at a fixed level above

the clamp voltage V

The output of C2 initiates

the timing one-shots for gating the sample and
hold circuits The sample of the sync tip is de-
layed by 0 8

ms to enable the actual sample of

ms to be taken on the optimum section of the

sync pulse tip The acquisition time of the circuit
is about three horizontal lines The double poly
CMOS technology enables long time constants to
be achieved with small high quality on-chip ca-
pacitors The back porch voltage is similarly de-
rived from the trailing edge of sync which also
serves to cut off the tip sample if the gate time
exceeds the tip period Note that the sample and
hold gating times will track RSET through I

The 50% level of the sync tip is derived through
the resistor divider R1 and R2 from the sample
and held voltages V

TIP

and V

and applied to

the plus input of comparator C1 This compara-
tor has built in hysteresis to avoid false trigger-
ing The output of C2 is a digital 5V signal which
feeds the C S ouput buffer B1 and the other in-
ternal circuit blocks the vertical back porch and
odd even functions

The vertical circuit senses the C S edges and ini-
tiates an integrator which is reset by the shorter
horizontal sync pulses but times out the longer

EL4581C

Sync Separator 50% Slice S-H Filter

Description of Operation

Contd

vertical sync pulse widths The internal timing
circuits are referenced to I

and V

the time-

out period being inversely proportional to the
timing current The vertical output pulse is start-
ed on the first serration pulse in the vertical in-
terval and is then self-timed out In the absense
of a serration pulse an internal timer will default
the start of vertical

The back porch is triggered from the sync tip
trailing edge and initiates a one-shot pulse The
period of this pulse is again a function of I

and

will therefore track the scan rate set by RSET

The odd even circuit (O E) comprises of flip
flops which track the relationship of the horizon-
tal pulses to the leading edge of the vertical out-
put and will switch on every field at the start of
vertical Pin 7 is high during the odd field

Loss of video signal can be detected by monitor-
ing the C S output The 50% level of the previ-
ous video signal will remain held on the S H ca-
pacitors after the input video signal has gone and
the input on pin 2 has defaulted to the clamp
voltage Consequently the C S output will re-
main low longer than the normal vertical pulse
period An external timing circuit could be used
to detect this condition

Block Diagram

4581 4

Figure 5

Note RSET must be a 1% resistor

EL4581C

January

1996

Rev

EL4581C

Sync Separator 50% Slice S-H Filter

General Disclaimer

Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement

Elantec Inc
1996 Tarob Court
Milpitas CA 95035
Telephone (408) 945-1323

(800) 333-6314

Fax (408) 945-9305

European Office 44-71-482-4596

WARNING

Life Support Policy

Elantec Inc products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec Inc Life Support systems are equipment in-
tended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death Users contemplating application of Elantec Inc products
in Life Support Systems are requested to contact Elantec Inc
factory headquarters to establish suitable terms

conditions for

these applications Elantec Inc 's warranty is limited to replace-
ment of defective components and does not cover injury to per-
sons or property or other consequential damages

Printed in U S A

Part Number EL4581C