General Description

The DS3904/DS3905 contain three nonvolatile (NV) low
temperature coefficient, variable digital resistors. Each
resistor has 128 user-selectable positions. Additionally,
the DS3904/DS3905 have a high-impedance setting that
allows each resistor to function as a digital switch. The
DS3904/DS3905 can operate over a 2.7V to 5.5V supply
voltage range, and communication with the device is
achieved through a 2-wire serial interface. Address pins
allow multiple DS3904/DS3905s to operate on the same
two-wire bus. The DS3904 has one address pin, allow-
ing two DS3904s to share the bus, while the DS3905
has three address pins, allowing up to eight DS3905s to
share a common bus. The low-cost and small size of the
DS3904/DS3905 make them ideal replacements for con-
ventional mechanical trimming resistors.

Applications

Power-Supply Calibration

Cell Phones and PDAs

Fibre Optic Transceiver Modules

Portable Electronics

Small and Low-Cost Replacement for
Conventional Mechanical Trimming Resistors/
Dip Switches

Test Equipment

Features

Three 20k, 128-Position Linear Digital Resistors
Resistor Settings are Stored in NV Memory
Each Resistor has a High-Impedance Setting for

Switch Operation to Control Digital Logic

Low Temperature Coefficient
2-Wire Serial Interface
2.7V to 5.5V Operating Range
-40°C to +85°C Industrial Temperature
Packaging: 8-Pin µSOP for DS3904, 10-pin µSOP

for DS3905

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

_____________________________________________ Maxim Integrated Products

SDA

TOP VEIW

SCL

µSOP

GND

DS3904

SDA

µSOP

SDL

GND

DS3905

Pin Configurations

0.1

µF

4.7k

2-WIRE

MASTER

RHIZ

SCL

SDA

(DS3905 ONLY)

RESISTOR 0
20k

ADDR F8h

RESISTOR 1
20k

ADDR F9h

RESISTOR 2
20k

ADDR FAh

GND

4.7k

VARIABLE RESISTANCE
FOR ADJUSTABLE
CURRENT SOURCE

INTERFACE EXAMPLES

2-WIRE
ADDRESSABLE
SWITCH (USING 00h
AND RHIZ SETTINGS)

GAIN
CONTROL

DS3904/DS3905

RHIZ

DIGITAL
LOGIC

Typical Operating Circuit

Ordering Information

Rev 1; 8/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

PART

TEMP RANGE

PIN-
PACKAGE

RESISTANCE

DS3904U-020

-40

°C to +85°C 8 µSOP

20k

+ Hi-Z

DS3905U-020

-40

°C to +85°C 10 µSOP

20k

+ Hi-Z

DS3904/DS3905

Triple 128-Position Nonvolatile
Variable Digital Resistor/Switch

______________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

= -40°C to +85°C)

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage on V

Pin Relative to Ground.................-0.5V to +6.0V

Voltage on SDA, SCL, A0, A1, A2

Relative to Ground*...................................-0.5V to V

+ 0.5V

Voltage on H0, H1, and

H2 Relative to Ground .......................................-0.5V to +6.0V

Current Through H0, H1, and H2..........................................3mA

Operating Temperature Range ...........................-40

°C to +85°C

Programming Temperature Range .........................0

°C to +70°C

Storage Temperature Range .............................-55

°C to +125°C

Soldering Temperature ................See J-STD-020A Specification

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

(Note 1)

2.7

5.5

Input Logic 1

0.7 x

0.3

Input Logic 0

-0.3

0.3 x

Resistor Current

Resistor Terminals H0, H1, H2

= +2.7V to +5.5V

-0.3

+5.5

DC ELECTRICAL CHARACTERISTICS

= +2.7V to +5.5V, T

= -40°C to +85°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Leakage

(Note 2)

-1

µA

= 3V (Note 3)

200

Standby Supply Current

STBY

= 5V (Note 3)

145

200

µA

OL1

3mA sink current

0.4

Low-Level Output Voltage (SDA)

OL2

6mA sink current

0.6

ANALOG RESISTOR CHARACTERISTICS

= +2.7V to +5.5V, T

= -40°C to +85°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Absolute Linearity

(Note 4)

-1

LSB

Relative Linearity

(Note 5)

-0.5

+0.5

LSB

Temperature Coefficient

Position 7Fh (Note 6)

-200

+123

+400

ppm/°C

Position 7Fh Resistance

MAX

= +25°C

14.5

25.5

Position 00h Resistance

MIN

= +25°C

200

500

High Impedance

HI-Z

5.5

*This voltage must not exceed 6.0V.

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

_____________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

= +2.7V to +5.5V, T

= -40°C to +85°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Fast mode

400

SCL Clock Frequency
(Note 7)

SCL

Standard mode

100

kHz

Fast mode

1.3

Bus Free Time between STOP
and START Conditions (Note 7)

BUF

Standard mode

4.7

µs

Fast mode

0.6

Hold Time (Repeated) START
Condition (Notes 7, 8)

HD:STA

Standard mode

4.0

µs

Fast mode

1.3

Low Period of SCL Clock
(Note 7)

LOW

Standard mode

4.7

µs

Fast mode

0.6

High Period of SCL Clock
(Note 7)

HIGH

Standard mode

4.0

µs

Fast mode

0.9

Data Hold Time
(Notes 7, 9)

HD:DAT

Standard mode

0.9

µs

Fast mode

100

Data Setup Time
(Note 7)

SU:DAT

Standard mode

250

Fast mode

0.6

Start Setup Time

SU:STA

Standard mode

4.7

µs

Fast mode

20 + 0.1C

300

Rise Time of Both SDA and SCL
Signals (Note 10)

Standard mode

20 + 0.1C

1000

Fast mode

20 + 0.1C

300

Fall Time of Both SDA and SCL
Signals (Note 10)

Standard mode

20 + 0.1C

300

Fast mode

0.6

Setup Time for STOP Condition

SU:STO

Standard mode

4.0

µs

Capacitive Load for Each Bus
Line

(Note 10)

400

EEPROM Write Time

(Note 11)

Startup Time

NONVOLATILE MEMORY CHARACTERISTICS

= +2.7V to +5.5V, T

= +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

EEPROM Writes

50,000

DS3904/DS3905

Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch

______________________________________________________________________

Note 1:

All voltages are referenced to ground.

Note 2:

Applies to A0, SDA, SCL for the DS3904 and A0, A1, A2, SDA, SCL for the DS3905. Also applies to H0, H1,
H2 for both DS3904 and DS3905 when in the high-impedance state.

Note 3:

STBY

specified with SDA = SCL = V

and A0 = GND.

Note 4:

Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation
from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at
position 7Fh.

Note 5:

Relative linearity is used to determine the change of resistance between two adjacent resistor positions.

Note 6:

Temperature coefficient specifies the change in resistance as a function of temperature. The temperature
coefficient varies with resistor position. Limits are guaranteed by design.

Note 7:

A fast-mode device can be used in a standard-mode system, but the requirement t

SU:DAT

> 250ns must

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line t

RMAX

+ t

SU:DAT

= 1000ns + 250ns =1250ns before the SCL line is released.

Note 8:

After this period, the first clock pulse is generated.

Note 9:

The maximum t

HD:DAT

has only to be met if the device does not stretch the LOW period (t

LOW

) of the SCL

signal.

Note 10:

--total capacitance of one bus line in picofarads, timing referenced to 0.9 x V

and 0.1 x V

Note 11:

EEPROM write begins after a stop condition occurs.

NONVOLATILE MEMORY CHARACTERISTICS (continued)

= +2.7V to +5.5V, T

= +70°C.)

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

_____________________________________________________________________

Typical Operating Characteristics

= +5.0V, T

= +25°C, unless otherwise noted.)

RESISTANCE

vs. RESISTOR SETTING

DS3904/5 toc03

RESISTOR SETTING (DEC)

RESISTANCE (k

)

125

100

RESISTORS
0, 1, AND 2

SUPPLY CURRENT

vs. SCL FREQUENCY

DS3904/5 toc02

SCL FREQUENCY (kHz)

SUPPLY CURRENT (

350

300

200 250

100 150

100

120

140

160

180

200

400

= SDA = +5V

ADDRESS PINS
CONNECTED TO GND

SUPPLY CURRENT

vs. TEMPERATURE

DS3904/5 toc01

TEMPERATURE (

°C)

SUPPLY CURRENT (

-20

100

120

140

160

-40

= +5V

= +3V

SDA = SCL =V

ADDRESS PINS
CONNECTED TO GND

POSITION 00h RESISTANCE PERCENT

CHANGE FROM +25

°C vs. TEMPERATURE

DS3904/5 toc06

TEMPERATURE (

°C)

RESISTANCE % CHANGE (FROM 25

°
C)

-20

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-2.5

-40

RESISTORS 0, 1, AND 2

POSITION 7Fh RESISTANCE PERCENT

CHANGE FROM +25

°C vs. TEMPERATURE

DS3904/5 toc05

TEMPERATURE (

°C)

RESISTANCE % CHANGE (FROM 25

°
C)

-20

-0.2

0.2

0.4

0.6

0.8

1.0

-0.4

-40

RESISTORS 0, 1, AND 2

TEMPERATURE COEFFICIENT

vs. RESISTOR SETTING

DS3904/5 toc04

RESISTOR SETTING (DEC)

TEMPERATURE COEFFICIENT (ppm/

°
C)

100

200

300

400

500

600

-100

120

TC OF +25

°C TO +85°C

TC OF +25

°C TO -40°C

RESISTORS
0, 1, AND 2

POSITION 3Fh RESISTANCE

vs. SUPPLY VOLTAGE

DS3904/5 toc09

SUPPLY VOLTAGE (V)

POSITION 3Fh RESISTANCE (k

)

5.5

5.0

4.5

4.0

3.5

3.0

10.5

11.0

11.5

12.0

12.5

13.0

10.0

2.5

6.0

RESISTORS
0, 1, AND 2

RESISTANCE

vs. POWER-DOWN VOLTAGE

DS3904/5 toc08

POWER-DOWN VOLTAGE (V)

RESISTANCE (k

)

100

POSITION 3Fh

RESISTORS

0, 1, AND 2

PROGRAMMED

RESISTANCE

>5.5M

RESISTANCE

vs. POWER-UP VOLTAGE

DS3904/5 toc07

POWER-UP VOLTAGE (V)

RESISTANCE (k

)

100

>5.5M

POSITION 3Fh

RESISTORS

0, 1, AND 2

EEPROM

RECALL

PROGRAMMED

RESISTANCE

DS3904/DS3905

Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch

______________________________________________________________________

ABSOLUTE LINEARITY

vs. RESISTOR 1 POSITION

DS3904/5 toc12

RESISTOR 1 POSITION (DEC)

ABSOLUTE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 1
20k

RELATIVE LINEARITY

vs. RESISTOR 0 POSITION

DS3904/5 toc11

RESISTOR 0 POSITION (DEC)

RELATIVE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 0
20k

ABSOLUTE LINEARITY

vs. RESISTOR 0 POSITION

DS3904/5 toc10

RESISTOR 0 POSITION (DEC)

ABSOLUTE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 0
20k

RELATIVE LINEARITY

vs. RESISTOR 2 POSITION

DS3904/5 toc15

RESISTOR 2 POSITION (DEC)

RELATIVE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 2
20k

ABSOLUTE LINEARITY

vs. RESISTOR 2 POSITION

DS3904/5 toc14

RESISTOR 2 POSITION (DEC)

ABSOLUTE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 2
20k

RELATIVE LINEARITY

vs. RESISTOR 1 POSITION

DS3904/5 toc13

RESISTOR 1 POSITION (DEC)

RELATIVE LINEARITY (LSB)

120

100

0.02

0.04

0.06

0.08

0.10

RESISTOR 1
20k

Typical Operating Characteristics (continued)

= +5.0V, T

= +25°C, unless otherwise noted.)

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

_____________________________________________________________________

Detailed Description

The DS3904/DS3905 contain three, 128-position, NV,
low temperature coefficient, variable digital resistors.
They are controlled through a 2-wire serial interface,
and can serve as a low-cost replacement for designs
using conventional trimming resistors. Furthermore, the
DS3904 address pin (A0) allows two DS3904s to be
placed on the same 2-wire bus. The three address pins
on the DS3905 allow up to eight DS3905s to be placed
on the same 2-wire bus.

With their low cost and small size, the DS3904/DS3905
are well tailored to replace larger mechanical trimming
variable resistors. This allows the automation of calibra-
tion in many instances because the 2-wire interface can
easily be adjusted by test/production equipment.

Variable Resistor Memory Organization

The variable resistors of the DS3904/DS3905 are
addressed by communicating with the registers in
Table 1.

Using the Resistor as a Switch

By taking advantage of the high-impedance mode, a
switch can be created to produce a digital output.
Setting a resistor register to 00h creates the low state.
Writing 80h into the same resistor register enables the
high-impedance state. When used with an external
pullup resistor, such as a 4.7k

pullup, a high state

is generated.

Device Operation

Clock and Data Transitions

The SDA pin is normally pulled high with an external
resistor or device. Data on the SDA pin can only change
during SCL low time periods. Data changes during SCL
high periods indicate a start or stop condition depend-
ing on the conditions discussed below. See the timing
diagrams for further details (Figures 2 and 3).

Start Condition

A high-to-low transition of SDA with SCL high is a start
condition, which must precede any other command. See
the timing diagrams for further details (Figures 2 and 3).

Stop Condition

A low-to-high transition of SDA with SCL high is a stop
condition. After a read or write sequence, the stop com-
mand places the DS3904/DS3905 into a low-power
mode. See the timing diagrams for further details
(Figures 2 and 3).

Acknowledge

All address and data bytes are transmitted through a
serial protocol. The DS3904/DS3905 pull the SDA line
low during the ninth clock pulse to acknowledge that
they have received each byte.

Standby Mode

The DS3904/DS3905 feature a low-power mode that is
automatically enabled after power-on, after a stop com-
mand, and after the completion of all internal operations.

Pin Description

PIN

NAME

DS3904

DS3905

DESCRIPTION

SDA

2-Wire Serial Data. Open-drain
input/output for 2-wire data.

SCL

2-Wire Serial Clock. Input for
2-wire clock.

Supply Voltage Terminal

GND

Ground Terminal

Resistor 2 High Terminals

Resistor 1 High Terminals

Resistor 0 High Terminals

Address-Select Pin

Ad d r ess- S el ect P i n ( D S 3905 Onl y)

Table 1. Variable Resistor Registers

ADDRESS

VARIABLE
RESISTOR

POSITION 7Fh

RESISTANCE

NUMBER OF

POSITIONS*

F8h

Resistor 0

20k

(nominal)

128 (00h to

7Fh) + Hi-Z

F9h

Resistor 1

20k

(nominal)

128 (00h to

7Fh) + Hi-Z

FAh

Resistor 2

20k

(nominal)

128 (00h to

7Fh) + Hi-Z

*Writing a value greater than 7Fh to any of the resistor registers
sets the high-impedance mode control bit (RHIZ, the MSB of
the resistor register) resulting in the resistor going into high-
impedance mode. Position 0 is the minimum position. Position
127 is the maximum position.

DS3904/DS3905

Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch

______________________________________________________________________

Bus Reset

After any interruption in protocol, power loss, or system
reset, the following steps reset the DS3904/DS3905:

Clock up to nine cycles.

Look for SDA high in each cycle while SCL is high.

Create a start condition while SDA is high.

Device Addressing

The DS3904/DS3905 must receive an 8-bit device
address byte following a start condition to enable a
specific device for a read or write operation. The
address byte is clocked into the DS3904/DS3905 MSB
to LSB. For the DS3904, the address byte consists of
101000 binary followed by A0 then the R/W bit. If the
R/W bit is high, a read operation is initiated. For the
DS3905, the address byte consists of 1010 binary fol-
lowed by A2, A1, A0 then the R/W bit. If the R/W bit is
low, a write operation is initiated. For a device to
become active, the value of the address bits must be
the same as the hard-wired address pins on the
DS3904/DS3905. Upon a match of written and hard-
wired addresses, the DS3904/DS3905 output a zero for
one clock cycle as an acknowledge. If the address
does not match, the DS3904/DS3905 return to a low-
power mode.

Write Operations

After receiving a matching device address byte with the
R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM
memory address to the device to define the address

where the data is to be written. After the byte has been
received, the DS3904/DS3905 transmit a zero for one
clock cycle to acknowledge that the memory address
has been received. The master must then transmit an 8-
bit data word to be written into this memory address. The
DS3904/DS3905 again transmit a zero for one clock
cycle to acknowledge the receipt of the data byte. At this
point, the master must terminate the write operation with
a stop condition. The DS3904/DS3905 then enter an
internally timed write process t

to the EEPROM memo-

ry. All inputs are disabled during this write cycle.

Acknowledge Polling

Once a EEPROM write is initiated, the part will not
acknowledge until the cycle is complete. Another
option is to wait the maximum write cycle delay before
initiating another write cycle.

Read Operations

After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. A read requires a dummy byte write sequence to
load in the register address. Once the device address
and data address bytes are clocked in by the master,
and acknowledged by the DS3904/ DS3905, the master
must generate another start condition (repeated start).
The master now initiates a read by sending the device
address with the R/W bit set high. The DS3904/DS3905
acknowledge the device address and serially clock out
the data byte. The master responds with a NACK and
generates a stop condition afterwards.

See Figures 4 and 5 for command and data byte struc-
tures as well as read and write examples.

2-Wire Serial Port Operation

The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a master. The
devices that are controlled by the master are slaves. The
bus must be controlled by a master device that gener-
ates the SCL, controls the bus access, and generates
the start and stop conditions. The DS3904/DS3905 oper-
ate as slaves on the 2-wire bus. Connections to the bus
are made through SCL and open-drain SDA lines. The
following I/O terminals control the 2-wire serial port: SDA,
SCL, and A0. The DS3905 uses two additional address
pins A1 and A2 to control the 2-wire serial port. Timing
diagrams for the 2-wire serial port can be found in
Figures 2 and 3. Timing information for the 2-wire serial
port is provided in the AC Electrical Characteristics table
for 2-wire serial communications.

2-WIRE

INTERFACE

RHIZ CONTROL

EEPROM

RES 0
20k

F8h

MSB

LSB

DATA

GND

SCL

SDA

DS3905

RESISTOR 0

RHIZ CONTROL

RES 1
20k

F9h

MSB

LSB

RESISTOR 1

RHIZ CONTROL

RES 2
20k

FAh

MSB

LSB

RESISTOR 2

(DS3905 ONLY)

Figure 1. DS3904/DS3905 Block Diagram

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

_____________________________________________________________________

The following bus protocol has been defined:

Data transfer can be initiated only when the bus is
not busy.

During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted
as control signals.

Accordingly, the following bus conditions have been
defined:

Bus Not Busy: Both data and clock lines remain
high.

Start Data Transfer: A change in the state of the
data line from high to low while the clock is high
defines a start condition.

Stop Data Transfer: A change in the state of the
data line from low to high while the clock line is
high defines the stop condition.

Data Valid: The state of the data line represents
valid data when, after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line can be changed
during the low period of the clock signal. There is

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

Figure 2. 2-Wire Data Transfer Protocol

SDA

SCL

HD:STA

LOW

HIGH

HD:DAT

SU:DAT

REPEATED

START

SU:STA

HD:STA

SU:STO

STOP

START

BUF

Figure 3. 2-Wire AC Characteristics

DS3904/DS3905

Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch

_____________________________________________________________________

one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-
wire bus. Depending upon the state of the R/W bit,
two types of data transfer are possible.

Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between start and stop
conditions is not limited and is determined by the
master device. The information is transferred byte-
wise and each receiver acknowledges with a ninth
bit.

Within the bus specifications, a regular mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS3904/DS3905 work in both
modes.

Acknowledge: Each receiving device, when
addressed, generates an acknowledge after the
byte has been received. The master device must
generate an extra clock pulse that is associated
with this acknowledge bit.

A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is a stable low during
the high period of the acknowledge-related clock
pulse. Of course, setup and hold times must be
taken into account. A master must signal an end of
data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out
of the slave. In this case, the slave must leave the
data line high to enable the master to generate the
stop condition.

Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows a
number of data bytes. The slave returns an
acknowledge bit after each received byte.

Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then
returns an acknowledge bit. Next follows the data
byte transmitted by the slave to the master. The
master returns NACK followed by a stop.

The master device generates all serial clock pulses
and the start and stop conditions. A transfer is
ended with a stop condition or with a repeated start
condition. Since a repeated start condition is also
the beginning of the next serial transfer, the bus is
not released.

MSB

START

LSB

COMMAND BYTE

*DS3904, USE 0's INSTEAD OF A2 AND A1 FOR THE DEVICE ADDRESS

DEVICE IDENTIFIER

"FAMILY CODE"

SLAVE

ADDRESS

A2* A1* A0 R/W

MSB

LSB

DATA BYTE

RHIZ

CONTROL BIT

RESISTOR SETTING

Figure 4. Command and Data Byte Structures

MSB

A0h

A1h

F8h

F9h

FAh

00h

80h

7Fh

F9h

LSB

START

MSB

LSB

ACK

MSB

LSB

START

MSB

LSB

ACK

STOP

ACK

MSB

LSB

START

MSB

LSB

ACK

STOP

ACK

MSB

LSB

START

MSB

LSB

ACK

READ RESISTOR 1 VALUE

A0 = GND FOR DS3904
A0, A1, A2 = GND FOR DS3905

WRITE RESISTOR 0

TO MIN POSITION

MSB

LSB

REPEATED

START

MSB

LSB

ACK

STOP

NACK

FROM
SLAVE

MASTER

STOP

MSB

LSB

ACK

MSB

LSB

ACK

MSB

LSB

ACK

SET RESISTOR 1 TO Hi-Z

WRITE RESISTOR 2 TO

MAX POSITION

EXAMPLE 2-WIRE TRANSACTIONS

RESISTOR DATA

Figure 5. Example 2-Wire Transactions

DS3904/DS3905

Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11

Printed USA

is a registered trademark of Maxim Integrated Products.

The DS3904/DS3905 can operate in the following three
modes:

Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit has been
received.

Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3904/DS3905 while
the serial clock is input on SCL. Start and stop con-
ditions are recognized as the beginning and end of
a serial transfer.

Slave Address: The command/control byte is the
first byte received following the start condition from
the master device. The command/control byte con-
sists of a 4-bit device identifier. For the DS3904, the
identifier is followed by the device-select bits 0, 0,
and A0. For the DS3905, the identifier is followed by
the device-select bits A2, A1, A0. The device identi-
fier is used by the master device to select which
device is to be accessed. When reading or writing
the DS3904/DS3905, the device-select bits must
match the device-select pin(s). The last bit of the
command/control byte (R/W) defines the operation
to be performed. When set to a `1', a read operation
is selected, and when set to a `0', a write operation
is selected.

Following the start condition, the DS3904/DS3905 moni-
tor the SDA bus checking the device-type identifier
being transmitted. Upon receiving the control code, the
appropriate device address bit, and the read/write bit,
the slave device outputs an acknowledge signal on the
SDA line.

Applications Information

Power-Supply Decoupling

To achieve the best results when using the DS3904/
DS3905, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surface-
mount capacitor. Surface-mount components minimize
lead inductance, which improves performance, and
ceramic capacitors tend to have adequate high-fre-
quency response for decoupling applications.

High Resistor Terminal Voltage

It is possible to have a voltage on the resistor-high termi-
nals that is higher than the voltage connected to V

For instance, connecting V

to 3.0V while one or more

of the resistor high terminals are connected to 5.0V
allows a 3V system to control a 5V system. The 5.5V
maximum still applies to the limit on the resistor high ter-
minals regardless of the voltage present on V

Chip Information

TRANSISTOR COUNT: DS3904: 6905

DS3905: 6921

SUBSTRATE CONNECTED TO GROUND

Package Information

For the latest package outline information, go to www.maxim-ic.
com/packages.

Part Number DS3904