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REV: 011204

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata

FEATURES

§ Integrated NV SRAM, Real-Time Clock

(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source

§ Clock Registers are Accessed Identically to

the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.

§ Century Byte Register (Y2K Compliant)
§ Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

§ BCD-Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100

§ Battery Voltage-Level Indicator Flag
§ Power-Fail Write Protection Allows for ±10%

Power-Supply Tolerance

§ Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until
Power is Applied for the First Time

§ DIP Module Only:

Standard JEDEC Byte-Wide 512k x 8 Static

RAM Pinout

§ PowerCap

Module Board Only:

Surface-Mountable Package for Direct

Connection to PowerCap Containing
Battery and Crystal

Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities

of DS174xP Timekeeping RAM

§ Also Available in Industrial Temperature

Range: -40°C to +85°C

PIN CONFIGURATIONS

DS1747/DS1747P

Y2K-Compliant, Nonvolatile Timekeeping RAMs

www.maxim-ic.com

PowerCap is a registered trademark of Dallas Semiconductor.

A17

A18

1
2
3
4
5
6
7
8
9
10
11
12

Encapsulated DIP

(512k x 8)

A14

A5
A4
A3
A2
A1
A0

DQ1

DQ0

A15

WE
A13
A8
A9
A11
OE
A10
CE
DQ7

DQ5

DQ6

30
29
28
27
26
25
24
23
22
21

A16

A12

DQ2

GND

15
16

18
17

DQ4
DQ3

Dallas

Semiconductor

DS1747

N.C.

A15

A16

RST

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

A17

A14

A13

A12

A11

A10

A18

GND

BAT

PowerCap Module Board

(Uses DS9034PCX PowerCap)

Dallas

Semiconductor

DS1747P

TOP VIEW

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PIN DESCRIPTION

A0A18

Address

Input

Chip Enable

Output Enable

Write Enable

Power-Supply

Input

GND

Ground

DQ0DQ7 Data Input/Output
N.C.

No Connection

RST

Power-On Reset Output (PowerCap Module board only)

X1, X2

Crystal Connection

BAT

Battery Connection

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

TOP MARK

DS1747-70

0°C to +70°C

32 EDIP (0.740a)

DS1747-70

DS1747-70IND

-40°C to +85°C

32 EDIP (0.740a)

DS1747-70 IND

DS1747P-70

0°C to +70°C

34 PowerCap

DS1747P-70

DS1747P-70IND

-40°C to +85°C

34 PowerCap

DS1747P-70 IND

DS1747W-120

0°C to +70°C

32 EDIP (0.740a)

DS1747W-120

DS1747W-120IND

-40°C to +85°C

32 EDIP (0.740a)

DS1747W-120 IND

DS1747WP-120

0°C to +70°C

34 PowerCap

DS1747WP-120

DS1747WP-120IND

-40°C to +85°C

34 PowerCap

DS1747WP-120 IND

DESCRIPTION

The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can
occur during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1747 also contains
its own power-fail circuitry that deselects the device when the V

supply is in an out-of-tolerance

condition. This feature prevents loss of data from unpredictable system operation brought on by low V

as errant access and update cycles are avoided.

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Figure 1. Block Diagram

PACKAGES

The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers. The part number for the
PowerCap is DS9034PCX.

CLOCK OPERATIONS--READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see
Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500

ms to ensure the external registers will be updated.

Dallas

Semiconductor

DS1747

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 1. Truth Table

CE OE WE

MODE DQ POWER

X X

Deselect

High-Z

Standby

X V

Write

Data

Active

Read Data

Out Active

Read

High-Z Active

X X X

Deselect

High-Z CMOS

Standby

X X X

Deselect

High-Z

Data-Retention

Mode

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date
and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the
actual clock counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The

OSC bit is the MSB (bit 7) of the seconds registers,

see Table 2. Setting it to a one stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic "1" and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,

CE low, OE low, WE high, and address for seconds register remain valid and

stable).

CLOCK ACCURACY (DIP MODULE)

The DS1747 is guaranteed to keep time accuracy to within

±1 minute per month at 25°C. The RTC is

calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not
require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. The electrical environment also affects the clock accuracy, and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please
refer to Application Note 58.

CLOCK ACCURACY (PowerCap MODULE)

The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within

±1.53 minutes per month (35 ppm) at 25°C. Clock

accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58.

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 2. Register Map

DATA

ADDRESS

B7 B6 B5 B4 B3 B2 B1 B0

FUNCTION RANGE

7FFFF 10

Year

Year Year

00-99

7FFFE X X X

Month

01-12

7FFFD X X

Date

01-31

7FFFC BF FT X X X

Day

Day 01-07

7FFFB X X

Hour

Hour Hour

00-23

7FFFA X

Minutes

00-59

7FFF9

OSC

10 Seconds

Seconds

00-59

7FFF8 W R 10

Century

Century Century

00-39

OSC = Stop Bit

R = Read Bit

FT = Frequency Test

W = Write Bit

X = See Note

BF = Battery Flag

NOTE: All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1747 is in the read mode whenever

OE (output enable) is low, WE (write enable) is high, and CE

(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t

after the last address input is

stable, providing that the

CE and OE access times and states are satisfied. If CE or OE access times and

states are not met, valid data will be available at the latter of chip-enable access (t

CEA

)

or at output enable

access time (t

OEA

)

. The state of the data input/output pins (DQ) is controlled by

CE and OE. If the

outputs are activated before t

, the data lines are driven to an intermediate state until t

AA.

If the address

inputs are changed while

CE and OE remain valid, output data will remain valid for output data hold

time (t

) but will then go indeterminate until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1747 is in the write mode whenever

WE, and CE are in their active state. The start of a write is

referenced to the latter occurring transition of

WE or CE. The addresses must be held valid throughout

the cycle.

CE or WE must return inactive for a minimum of t

prior to the initiation of another read or

write cycle. Data in must be valid t

prior to the end of write and remain valid for t

afterward. In a

typical application, the

OE signal will be high during a write cycle. However, OE can be active provided

that care is taken with the data bus to avoid bus contention. If

OE is low prior to WE transitioning low

the data bus can become active with read data defined by the address inputs. A low transition on

will then disable the output t

WEZ

after

WE goes active.

Part Number DS1747